Commit b95c61e8 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Extend TXT Buffer validation with loading Identifier word.

parent 9b733646
Pipeline #11242 failed with stages
in 3 minutes and 13 seconds
......@@ -139,7 +139,10 @@ entity can_core is
-- TX Bit Rate Shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -482,6 +485,7 @@ begin
tran_ident_type => tran_ident_type, -- IN
tran_frame_type => tran_frame_type, -- IN
tran_brs => tran_brs, -- IN
tran_identifier => tran_identifier, -- IN
tran_frame_valid => tran_frame_valid, -- IN
txtb_hw_cmd => txtb_hw_cmd_i, -- IN
txtb_ptr => txtb_ptr, -- OUT
......
......@@ -165,6 +165,9 @@ entity protocol_control is
-- TX Bit rate shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -957,6 +960,7 @@ begin
is_err_active => is_err_active, -- IN
bst_ctr => bst_ctr, -- IN
tran_word => tran_word, -- IN
tran_identifier => tran_identifier, -- IN
tran_word_swapped => tran_word_swapped, -- IN
tran_dlc => tran_dlc -- IN
);
......
......@@ -158,6 +158,9 @@ entity tx_shift_reg is
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- TXT Buffer RAM word (byte endianity swapped)
tran_word_swapped :in std_logic_vector(31 downto 0);
......@@ -233,8 +236,8 @@ begin
stuff_count <= bst_ctr_grey & bst_parity;
-- Choosing Base and Ext IDs from TXT Buffer RAM memory words!
tx_base_id <= tran_word(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
tx_ext_id <= tran_word(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
tx_base_id <= tran_identifier(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
tx_ext_id <= tran_identifier(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
---------------------------------------------------------------------------
-- Shift register pre-load value:
......
......@@ -363,6 +363,9 @@ architecture rtl of can_top_level is
-- TX Frame Bit rate shift Flag
signal tran_brs : std_logic;
-- TX Identifier
signal tran_identifier : std_logic_vector(28 downto 0);
-- Word from TXT Buffer RAM selected by TX Arbitrator
signal tran_word : std_logic_vector(31 downto 0);
......@@ -651,6 +654,7 @@ begin
tran_ident_type => tran_ident_type, -- OUT
tran_frame_type => tran_frame_type, -- OUT
tran_brs => tran_brs, -- OUT
tran_identifier => tran_identifier, -- OUT
tran_frame_valid => tran_frame_valid, -- OUT
txtb_hw_cmd => txtb_hw_cmd, -- IN
txtb_changed => txtb_changed, -- OUT
......@@ -762,6 +766,7 @@ begin
tran_ident_type => tran_ident_type, -- IN
tran_frame_type => tran_frame_type, -- IN
tran_brs => tran_brs, -- IN
tran_identifier => tran_identifier, -- IN
tran_frame_valid => tran_frame_valid, -- IN
txtb_hw_cmd => txtb_hw_cmd, -- OUT
txtb_changed => txtb_changed, -- IN
......
......@@ -1917,7 +1917,10 @@ package can_components is
-- TX Bit rate shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -2442,6 +2445,9 @@ package can_components is
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- TXT Buffer RAM word (byte endianity swapped)
tran_word_swapped :in std_logic_vector(31 downto 0);
......@@ -2520,6 +2526,9 @@ package can_components is
-- TX Bit Rate Shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -3941,7 +3950,7 @@ package can_components is
-- CAN Core Interface
-----------------------------------------------------------------------
-- HW Commands from CAN Core for manipulation with TXT Buffers
txtb_hw_cmd :in t_txtb_hw_cmd;
txtb_hw_cmd :in t_txtb_hw_cmd;
---------------------------------------------------------------------------
-- TX Arbitrator FSM outputs
......@@ -3954,13 +3963,22 @@ package can_components is
-- Load Frame format word to metadata pointer
load_ffmt_w_addr :out std_logic;
-- Load identifier word to metadata pointer
load_ident_w_addr :out std_logic;
-- Store timestamp lower word
store_ts_l_w :out std_logic;
-- Store metadata (Frame format word) on the output of TX Arbitrator
store_md_w :out std_logic;
-- Store identifier (Identifier word) on the output of TX Arbitrator
store_ident_w :out std_logic;
-- Store metadata (Frame format word) to double buffer registers.
buffer_md_w :out std_logic;
-- Signals that TX Arbitrator is locked (CAN Core is transmitting from TXT
-- Buffer)
tx_arb_locked :out std_logic;
......@@ -4027,7 +4045,10 @@ package can_components is
-- TX Frame Bit rate shift Flag
tran_brs :out std_logic;
-- TX Identifier
tran_identifier :out std_logic_vector(28 downto 0);
-- There is valid frame selected, can be locked for transmission
tran_frame_valid :out std_logic;
......
......@@ -141,9 +141,12 @@ package can_types is
-- TX arbitrator state type
type t_tx_arb_state is (
s_arb_idle,
s_arb_sel_low_ts,
s_arb_sel_upp_ts,
s_arb_sel_ffw,
s_arb_sel_idw,
s_arb_validated,
s_arb_locked
);
......
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