Commit b1742887 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '316-stuff-counter-when-sof-is-not-transmitted' into 'master'

Resolve "Stuff counter when SOF is not transmitted"

Closes #316

See merge request !263
parents ec5c7391 8673e103
Pipeline #11575 passed with stage
in 17 seconds
......@@ -511,7 +511,7 @@ filename "version.tex"
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="3" columns="5">
<lyxtabular version="3" rows="4" columns="5">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="1.5cm">
<column alignment="center" valignment="top" width="3cm">
......@@ -614,13 +614,60 @@ Initial version - separated stand-alone architecture document from Datasheet
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0.2
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
2.2
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Ondrej Ille
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
29-09-2019
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TX Arbitrator loads identifier as part of TXT buffer validation.
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0.3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
......@@ -645,7 +692,7 @@ Ondrej Ille
\begin_inset Text
\begin_layout Plain Layout
29-09-2019
07-10-2019
\end_layout
\end_inset
......@@ -654,7 +701,7 @@ Ondrej Ille
\begin_inset Text
\begin_layout Plain Layout
TX Arbitrator loads identifier as part of TXT buffer validation.
Update interfaces
\end_layout
\end_inset
......@@ -981,12 +1028,10 @@ When CTU CAN FD GIT repository is clonned, register map can be generated
\end_layout
\begin_layout Verbatim
cd scripts
\end_layout
\begin_layout Verbatim
./update_reg_map
\end_layout
......@@ -999,12 +1044,10 @@ Documentation can be exported from VHDL RTL codes by following script:
\end_layout
\begin_layout Verbatim
cd scripts
\end_layout
\begin_layout Verbatim
python gen_lyx_tables.py --configPath vhdl_lyx_interface_cfg.yml
\end_layout
......@@ -1037,12 +1080,10 @@ CTU CAN FD contains release tags in GIT repository.
\end_layout
\begin_layout Verbatim
cd scripts
\end_layout
\begin_layout Verbatim
python create_release.py --output_dir ../release_directory_name
\end_layout
......@@ -1064,12 +1105,10 @@ src/component.xml
\end_layout
\begin_layout Verbatim
cd scripts
\end_layout
\begin_layout Verbatim
python gen_vivado_component.py
\end_layout
......
......@@ -260,8 +260,8 @@ Ports
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="15" columns="4">
<features tabularvalignment="middle">
<lyxtabular version="3" rows="16" columns="4">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
<column alignment="center" valignment="top" width="3.5cm">
......@@ -932,6 +932,44 @@ std_logic_vector
Length of Bit Stuffing rule
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_frame_no_sof
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
std_logic
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Frame transmission without SOF started
\end_layout
\end_inset
</cell>
</row>
......
......@@ -564,7 +564,7 @@ Ports
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="58" columns="4">
<lyxtabular version="3" rows="59" columns="4">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1330,6 +1330,48 @@ TX Bit Rate Shift
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_identifier
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(28 downto 0)
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TX Identifier
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_frame_valid
\end_layout
......
......@@ -374,7 +374,7 @@ Ports
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="107" columns="4">
<lyxtabular version="3" rows="109" columns="4">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
......@@ -1676,6 +1676,48 @@ TX Bit rate shift
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_identifier
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
in
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(28 downto 0)
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TX Identifier
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_frame_valid
\end_layout
......@@ -3749,6 +3791,44 @@ Bit Stuffing type (0-Normal, 1-Fixed)
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tx_frame_no_sof
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
out
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
std_logic
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Frame transmission without SOF started
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
stuff_length
\end_layout
......
......@@ -4365,6 +4365,40 @@ std_logic\end_layout
\begin_layout Plain Layout
Fixed Bit stuffing method\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
tx_frame_no_sof\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
out\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
std_logic\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Frame transmission without SOF started\end_layout
\end_inset
</cell>
</row>
......
......@@ -298,8 +298,8 @@ Ports
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="24" columns="4">
<features tabularvalignment="middle">
<lyxtabular version="3" rows="25" columns="4">
<features islongtable="true" longtabularalignment="center">
<column alignment="center" valignment="top" width="4cm">
<column alignment="center" valignment="top" width="1.2cm">
<column alignment="center" valignment="top" width="3.5cm">
......@@ -1098,6 +1098,48 @@ TX Frame Bit rate shift Flag
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_identifier
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
out
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
std_logic_vector
\begin_inset Newline newline
\end_inset
(28 downto 0)
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
TX Identifier
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
tran_frame_valid
\end_layout
......
......@@ -108,7 +108,10 @@ entity bit_stuffing is
fixed_stuff :in std_logic;
-- Length of Bit Stuffing rule
stuff_length :in std_logic_vector(2 downto 0);
stuff_length :in std_logic_vector(2 downto 0);
-- Frame transmission without SOF started
tx_frame_no_sof :in std_logic;
------------------------------------------------------------------------
-- Status signals
......@@ -327,11 +330,15 @@ begin
---------------------------------------------------------------------------
-- Next value for counter of equal consecutive bits:
-- 1. Reset
-- 2. Increment if not reset when processing bit.
-- 3. Keep original value otherwise.
---------------------------------------------------------------------------
same_bits_d <= "001" when (same_bits_rst = '1') else
-- 1. Set to 2 when transmission started without SOF and first bit of
-- Base ID is dominant! This accounts for SOF + Base ID (1)!
-- 2. Reset
-- 3. Increment if not reset when processing bit.
-- 4. Keep original value otherwise.
---------------------------------------------------------------------------
same_bits_d <= "010" when (tx_frame_no_sof = '1' and
data_in = DOMINANT) else
"001" when (same_bits_rst = '1') else
same_bits_add when (bst_trigger = '1') else
same_bits_q;
......
......@@ -335,6 +335,7 @@ architecture rtl of can_core is
signal stuff_enable : std_logic;
signal destuff_enable : std_logic;
signal fixed_stuff : std_logic;
signal tx_frame_no_sof : std_logic;
signal stuff_length : std_logic_vector(2 downto 0);
signal dst_ctr : std_logic_vector(2 downto 0);
signal bst_ctr : std_logic_vector(2 downto 0);
......@@ -538,6 +539,7 @@ begin
stuff_enable => stuff_enable, -- OUT
destuff_enable => destuff_enable, -- OUT
fixed_stuff => fixed_stuff, -- OUT
tx_frame_no_sof => tx_frame_no_sof, -- OUT
stuff_length => stuff_length, -- OUT
dst_ctr => dst_ctr, -- IN
bst_ctr => bst_ctr, -- IN
......@@ -718,6 +720,7 @@ begin
stuff_enable => stuff_enable, -- IN
fixed_stuff => fixed_stuff, -- IN
stuff_length => stuff_length, -- IN
tx_frame_no_sof => tx_frame_no_sof, -- IN
-- Status signals
bst_ctr => bst_ctr, -- OUT
......@@ -877,7 +880,7 @@ begin
----------------------------------------------------------------------------
stat_bus(511 downto 384) <= (OTHERS => '0');
stat_bus(299 downto 297) <= (OTHERS => '0');
stat_bus(187 downto 186) <= (OTHERS => '0');
stat_bus(187 downto 188) <= (OTHERS => '0');
stat_bus(98 downto 90) <= (OTHERS => '0');
stat_bus(60 downto 32) <= (OTHERS => '0');
stat_bus(113) <= '0';
......@@ -1132,7 +1135,12 @@ begin
stat_bus(STAT_RETR_CTR_HIGH downto STAT_RETR_CTR_LOW) <=
retr_ctr_i;
stat_bus(STAT_RX_TRIGGER) <=
rx_triggers(0);
stat_bus(STAT_TX_TRIGGER) <=
tx_trigger;
---------------------------------------------------------------------------
-- Internal signals to output propagation
......
......@@ -306,6 +306,9 @@ entity protocol_control is
-- Bit Stuffing type (0-Normal, 1-Fixed)
fixed_stuff :out std_logic;
-- Frame transmission without SOF started
tx_frame_no_sof :out std_logic;
-- Length of Bit Stuffing rule
stuff_length :out std_logic_vector(2 downto 0);
......@@ -762,6 +765,7 @@ begin
destuff_enable => destuff_enable, -- OUT
stuff_length => stuff_length, -- OUT
fixed_stuff => fixed_stuff_i, -- OUT
tx_frame_no_sof => tx_frame_no_sof, -- OUT
-- Operation control interface
is_transmitter => is_transmitter, -- IN
......
......@@ -411,7 +411,10 @@ entity protocol_control_fsm is
-- Fixed Bit stuffing method
fixed_stuff :out std_logic;
-- Frame transmission without SOF started
tx_frame_no_sof :out std_logic;
-----------------------------------------------------------------------
-- Operation control interface
-----------------------------------------------------------------------
......@@ -723,6 +726,10 @@ architecture rtl of protocol_control_fsm is
-- Blocking HW command for Unlock When Error frame request is active
signal block_txtb_unlock_due_error : std_logic;
-- No SOF transmitted
signal tx_frame_no_sof_d : std_logic;
signal tx_frame_no_sof_q : std_logic;
begin
tx_frame_ready <= '1' when (tran_frame_valid = '1' and drv_bus_mon_ena = '0')
......@@ -1365,6 +1372,7 @@ begin
stuff_enable_clear <= '0';
destuff_enable_set <= '0';
destuff_enable_clear <= '0';
tx_frame_no_sof_d <= '0';
-- Synchronisation control
perform_hsync <= '0';
......@@ -2147,7 +2155,10 @@ begin
-- is received, become receiver!
if (tx_frame_ready = '1' and go_to_suspend = '0') then
txtb_hw_cmd_d.lock <= '1';
set_transmitter_i <= '1';
set_transmitter_i <= '1';
if (rx_data_nbs = DOMINANT) then
tx_frame_no_sof_d <= '1';
end if;
elsif (rx_data_nbs = DOMINANT) then
set_receiver_i <= '1';
end if;
......@@ -2241,7 +2252,6 @@ begin
if (rx_data_nbs = DOMINANT and is_bus_off = '0') then
ctrl_ctr_pload_i <= '1';
ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
tx_load_base_id_i <= '1';
sof_pulse_i <= '1';
crc_enable <= '1';
end if;
......@@ -2249,6 +2259,11 @@ begin
if (tx_frame_ready = '1' and is_bus_off = '0') then
txtb_hw_cmd_d.lock <= '1';
set_transmitter_i <= '1';
tx_load_base_id_i <= '1';
if (rx_data_nbs = DOMINANT) then
tx_frame_no_sof_d <= '1';
end if;
elsif (rx_data_nbs = DOMINANT) then
set_receiver_i <= '1';
end if;
......@@ -2819,6 +2834,19 @@ begin
end if;
end process;
-----------------------------------------------------------------------
-- Frame transmission (transmitter) started without SOF!
-----------------------------------------------------------------------
tx_frame_no_sof_proc : process(clk_sys, res_n)
begin
if (res_n = G_RESET_POLARITY) then
tx_frame_no_sof_q <= '0';
elsif (rising_edge(clk_sys)) then
if (rx_trigger = '1') then
tx_frame_no_sof_q <= tx_frame_no_sof_d;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- Internal signals to output propagation
......@@ -2838,6 +2866,7 @@ begin
retr_ctr_clear <= retr_ctr_clear_i;
arbitration_lost <= arbitration_lost_i;
retr_ctr_add <= retr_ctr_add_i;
tx_frame_no_sof <= tx_frame_no_sof_q;
-- <RELEASE_OFF>
-----------------------------------------------------------------------
......
......@@ -591,7 +591,10 @@ package can_components is
-- Length of Bit Stuffing rule
stuff_length :in std_logic_vector(2 downto 0);
-- Frame transmission without SOF started
tx_frame_no_sof :in std_logic;
------------------------------------------------------------------------
-- Status signals
------------------------------------------------------------------------
......@@ -1717,6 +1720,9 @@ package can_components is
-- Fixed Bit stuffing method
fixed_stuff :out std_logic;
-- Frame transmission without SOF started
tx_frame_no_sof :out std_logic;
-----------------------------------------------------------------------
-- Operation control interface
-----------------------------------------------------------------------
......@@ -2058,6 +2064,9 @@ package can_components is
-- Bit Stuffing type (0-Normal, 1-Fixed)
fixed_stuff :out std_logic;
-- Frame transmission without SOF started
tx_frame_no_sof :out std_logic;
-- Length of Bit Stuffing rule
stuff_length :out std_logic_vector(2 downto 0);
......
......@@ -348,6 +348,10 @@ package drv_stat_pkg is
constant STAT_REC_TRIG : natural := 182;
constant STAT_SAMPLE_INDEX : natural := 184;
constant STAT_SAMPLE_SEC : natural := 185;
-- TX/RX triggers (with stuff bits included)
constant STAT_RX_TRIGGER : natural := 186;
constant STAT_TX_TRIGGER : natural := 187;
-- Arbitration lost capture
constant STAT_ALC_ID_FIELD_HIGH : natural := 296;
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- No Start of Frame feature test - frame transmission!
--
-- Verifies:
-- 1. When a dominant bit is sampled in Bus idle and a frame is available for
-- transmission, its transmission is started without transmitting SOF bit.
-- 2. When CTU CAN FD joins transmission without transmitting SOF bit, it
-- accounts SOF bit as transmitted dominant bit in number of equal conse-
-- cutive bits.
--
-- Test sequence:
-- 1. Configure both Nodes to one-shot mode.
-- 2. Insert CAN frames which have first 5 bits of identifier equal to zero to
-- both nodes. Check both nodes are Idle. Wait till Sample point in Node 1.
-- 3. Send Set ready command to both nodes. Wait until Node 1 is not in Bus
-- idle state. Check it is transmitting Base Identifier (NOT SOF)!
-- 4. Wait until sample point 5 times (5th bit of idetifier) in Node 1. Check
-- Node 1 is transmitting Recessive bit (Stuff bit).
-- 5. Wait until frame is over. Check frame was received OK, read it from
-- receiving node and verify it was received OK!
--------------------------------------------------------------------------------
-- Revision History:
-- 07.10.2019 Created file
--------------------------------------------------------------------------------
context work.ctu_can_synth_context;
context work.ctu_can_test_context;