Commit af7461d1 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added Benchmark project constraints for higher speed

synthesis.
parent 1716f1a0
......@@ -104,4 +104,8 @@ set_global_assignment -name VHDL_FILE ../../src/Buffers_Message_Handling/message
set_global_assignment -name VHDL_FILE ../../src/ID_transfer.vhd
set_global_assignment -name VHDL_FILE ../../src/CAN_top_level.vhd
set_global_assignment -name TCL_SCRIPT_FILE ../../scripts/resource_benchmark.tcl
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
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