Commit 9fd2277d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src, test: Fixes vol. 2

parent 70bb8cd2
Pipeline #8069 failed with stage
in 13 seconds
......@@ -63,7 +63,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -57,7 +57,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -102,7 +102,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -297,7 +296,12 @@ begin
-- Synchronisation chain for input signal
----------------------------------------------------------------------------
can_rx_sig_sync_inst : sig_sync
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_RESET_VALUE => RECESSIVE
)
port map(
res_n => res_n,
clk => clk_sys,
async => can_rx,
sync => can_rx_synced
......@@ -339,9 +343,9 @@ begin
-- Propagate measured transceiver delay to output so that it can be
-- read from Memory registers.
---------------------------------------------------------------------------
trv_delay(trv_delay'length - 1 downto trv_delay'length) <=
trv_delay(trv_delay'length - 1 downto trv_delay_i'length) <=
(OTHERS => '0');
trv_delay(trv_delay'length - 1 downto 0) <= trv_delay_i;
trv_delay(trv_delay_i'length - 1 downto 0) <= trv_delay_i;
---------------------------------------------------------------------------
......@@ -386,8 +390,8 @@ begin
----------------------------------------------------------------------------
shift_regs_rst_reg_inst : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '1'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '1'
)
port map(
-- Keep without reset! We can't use res_n to avoid reset recovery!
......@@ -446,7 +450,7 @@ begin
generic map(
G_RESET_POLARITY => G_RESET_POLARITY,
G_TX_CACHE_DEPTH => G_TX_CACHE_DEPTH,
G_TX_CACHE_RES_VAL => RECESSIVE
G_TX_CACHE_RST_VAL => RECESSIVE
)
port map(
clk_sys => clk_sys, -- IN
......
......@@ -75,7 +75,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -57,7 +57,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -109,7 +109,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -258,7 +257,7 @@ begin
----------------------------------------------------------------------------
trv_delay_ctr_add <= std_logic_vector(to_unsigned(
to_integer(unsigned(trv_delay_ctr_reg) + 1),
g_trv_delay_ctr_reg'length));
trv_delay_ctr_reg'length));
----------------------------------------------------------------------------
-- Register for transceiver delay measurement progress flag.
......
......@@ -59,7 +59,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -41,7 +41,7 @@
--------------------------------------------------------------------------------
--Purpose:
-- Bit destuffing circuit. Data sampled always with valid rx_trig signal.
-- Bit destuffing circuit. Data sampled always with valid bds_trigger signal.
-- Length of bitStuffing controlled via stuff_length input. Stuff error signa-
-- lises Error when the stuff rule is not valid (stuff_lenght+1) consecutive
-- bits of the same polarity. Signal destuffed indicates that current output
......@@ -87,7 +87,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -120,8 +119,8 @@ entity bit_destuffing is
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- RX Trigger (in Sample point, from Prescaler).
rx_trig : in std_logic;
-- Bit Destuffing Trigger (in Sample point, from Prescaler).
bds_trigger : in std_logic;
-- Bit Destuffing is enabled.
destuff_enable : in std_logic;
......@@ -215,8 +214,8 @@ begin
---------------------------------------------------------------------------
dff_ena_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -265,7 +264,7 @@ begin
-- 2. Store "fixed_stuff" configuration when data are processed
---------------------------------------------------------------------------
fixed_prev_d <= '0' when (enable_prev = '0') else
fixed_stuff when (rx_trig = '1') else
fixed_stuff when (bds_trigger = '1') else
fixed_prev_q;
......@@ -290,8 +289,8 @@ begin
---------------------------------------------------------------------------
dff_fixed_stuff_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -317,7 +316,7 @@ begin
-- 3. Keep otherwise
---------------------------------------------------------------------------
dst_bit_ctr_d <= 0 when (enable_prev = '0') else
dst_bit_ctr_add when (rx_trig = '1' and
dst_bit_ctr_add when (bds_trigger = '1' and
stuff_lvl_reached = '1' and
fixed_stuff = '0') else
dst_bit_ctr_q;
......@@ -347,8 +346,8 @@ begin
-- previous processed bit.
---------------------------------------------------------------------------
same_bits_erase <= '1' when (destuff_enable = '0' or enable_prev = '0') else
'1' when (rx_trig = '1' and discard_stuff_bit = '1') else
'1' when (rx_trig = '1' and
'1' when (bds_trigger = '1' and discard_stuff_bit = '1') else
'1' when (bds_trigger = '1' and
data_in /= prev_val_q and
fixed_stuff = '0') else
'0';
......@@ -367,7 +366,7 @@ begin
-- 3. Keep its value otherwise.
---------------------------------------------------------------------------
same_bits_d <= 1 when (same_bits_erase = '1') else
same_bits_add when (rx_trig = '1') else
same_bits_add when (bds_trigger = '1') else
same_bits_q;
......@@ -393,9 +392,9 @@ begin
-- 4. Keep value otherwise.
---------------------------------------------------------------------------
destuffed_d <= '0' when (destuff_enable = '0') else
'1' when (rx_trig = '1' and
'1' when (bds_trigger = '1' and
discard_stuff_bit = '1') else
'0' when (rx_trig = '1') else
'0' when (bds_trigger = '1') else
destuffed_q;
......@@ -404,8 +403,8 @@ begin
---------------------------------------------------------------------------
dff_destuffed_flag_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -422,7 +421,7 @@ begin
-- 1. Set when bit should be processed and stuff rule is violated.
-- 2. Cleared otherwise
---------------------------------------------------------------------------
error_reg_d <= '1' when (rx_trig = '1' and stuff_rule_violate = '1') else
error_reg_d <= '1' when (bds_trigger = '1' and stuff_rule_violate = '1') else
'0';
......@@ -431,8 +430,8 @@ begin
---------------------------------------------------------------------------
dff_error_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -451,8 +450,8 @@ begin
-- bit stuffing. TODO: IS THIS OK???
---------------------------------------------------------------------------
prev_val_d <= RECESSIVE when (destuff_enable = '1' and enable_prev = '0') else
RECESSIVE when (rx_trig = '1' and non_fix_to_fix_chng = '1') else
data_in when (rx_trig = '1') else
RECESSIVE when (bds_trigger = '1' and non_fix_to_fix_chng = '1') else
data_in when (bds_trigger = '1') else
prev_val_q;
......@@ -461,8 +460,8 @@ begin
---------------------------------------------------------------------------
dff_prev_val_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => RECESSIVE
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => RECESSIVE
)
port map(
arst => res_n,
......
......@@ -85,7 +85,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -118,8 +117,8 @@ entity bit_stuffing is
------------------------------------------------------------------------
-- Control signals
------------------------------------------------------------------------
-- TX Trigger for Bit Stuffing (in SYNC segment)
tx_trigger :in std_logic;
-- Bit Stuffing Trigger (in SYNC segment)
bst_trigger :in std_logic;
-- Bit Stuffing enabled. If not, data are only passed to the output
stuff_enable :in std_logic;
......@@ -235,8 +234,8 @@ begin
---------------------------------------------------------------------------
dff_ena_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -261,7 +260,7 @@ begin
-- 2. Store "fixed_stuff" configuration when data are processed
---------------------------------------------------------------------------
fixed_reg_nxt <= '0' when (enable_prev = '0') else
fixed_stuff when (tx_trigger = '1') else
fixed_stuff when (bst_trigger = '1') else
fixed_reg;
---------------------------------------------------------------------------
......@@ -271,8 +270,8 @@ begin
---------------------------------------------------------------------------
dff_fixed_stuff_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -296,7 +295,7 @@ begin
-- 3. Keep previous value otherwise.
---------------------------------------------------------------------------
stuff_ctr_nxt <= 0 when (enable_prev = '0') else
stuff_ctr_add when (tx_trigger = '1' and
stuff_ctr_add when (bst_trigger = '1' and
stuff_lvl_reached = '1' and
fixed_stuff = '0') else
stuff_ctr;
......@@ -337,7 +336,7 @@ begin
-- 2. When processing bit and should be restarted by dedicated signal.
---------------------------------------------------------------------------
same_bits_rst <= '1' when (enable_prev = '0') or
(tx_trigger = '1' and same_bits_rst_trig = '1')
(bst_trigger = '1' and same_bits_rst_trig = '1')
else
'0';
......@@ -356,7 +355,7 @@ begin
-- 3. Keep original value otherwise.
---------------------------------------------------------------------------
same_bits_nxt <= 1 when (same_bits_rst = '1') else
same_bits_add when (tx_trigger = '1') else
same_bits_add when (bst_trigger = '1') else
same_bits;
......@@ -410,15 +409,15 @@ begin
-- 4. Keep previous value otherwise
---------------------------------------------------------------------------
data_out_nxt_ena <= RECESSIVE when (enable_prev = '0') else
(not data_out_int) when (tx_trigger = '1' and insert_stuff_bit = '1') else
data_in when (tx_trigger = '1') else
(not data_out_int) when (bst_trigger = '1' and insert_stuff_bit = '1') else
data_in when (bst_trigger = '1') else
data_out_int;
data_out_nxt <= data_out_nxt_ena when (stuff_enable = '1') else
data_in when (tx_trigger = '1') else
data_in when (bst_trigger = '1') else
data_out_int;
data_out_load <= '1' when (stuff_enable = '1' or tx_trigger = '1') else
data_out_load <= '1' when (stuff_enable = '1' or bst_trigger = '1') else
'0';
---------------------------------------------------------------------------
......@@ -428,8 +427,8 @@ begin
---------------------------------------------------------------------------
dff_data_out_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => RECESSIVE
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => RECESSIVE
)
port map(
arst => res_n,
......@@ -451,8 +450,8 @@ begin
-- 3. Erase when bit is processed, but stuff bit is not inserted.
---------------------------------------------------------------------------
halt_reg_nxt <= '0' when (enable_prev = '0' or stuff_enable = '0') else
'1' when (tx_trigger = '1' and insert_stuff_bit = '1') else
'0' when (tx_trigger = '1') else
'1' when (bst_trigger = '1' and insert_stuff_bit = '1') else
'0' when (bst_trigger = '1') else
halt_reg;
---------------------------------------------------------------------------
......@@ -460,8 +459,8 @@ begin
---------------------------------------------------------------------------
dff_halt_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......
......@@ -60,7 +60,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -63,7 +63,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -418,6 +417,8 @@ architecture rtl of can_core is
signal is_suspend : std_logic;
signal is_overload : std_logic;
signal sof_pulse_i : std_logic;
begin
----------------------------------------------------------------------------
......@@ -483,7 +484,7 @@ begin
rec_abort => rec_abort, -- OUT
store_data => store_data, -- OUT
store_data_word => store_data_word, -- OUT
sof_pulse => sof_pulse, -- OUT
sof_pulse => sof_pulse_i, -- OUT
-- Operation control FSM Interface
is_transmitter => is_transmitter, -- IN
......@@ -511,6 +512,7 @@ begin
-- CAN Bus serial data stream
tx_data_nbs => pc_tx_data_nbs, -- OUT
tx_data_wbs => tx_data_wbs_i,
rx_data_nbs => pc_rx_data_nbs, -- IN
-- Bit Stuffing Interface
......@@ -680,7 +682,7 @@ begin
data_out => bst_data_out, -- OUT
-- Control signals
tx_trigger => bst_trigger, -- IN
bst_trigger => bst_trigger, -- IN
stuff_enable => stuff_enable, -- IN
fixed_stuff => fixed_stuff, -- IN
stuff_length => stuff_length, -- IN
......@@ -707,7 +709,7 @@ begin
data_out => bds_data_out, -- OUT
-- Control signals
rx_trig => bds_trigger, -- IN
bds_trigger => bds_trigger, -- IN
destuff_enable => destuff_enable, -- IN
stuff_error_enable => stuff_error_enable, -- IN
fixed_stuff => fixed_stuff, -- IN
......@@ -807,8 +809,8 @@ begin
---------------------------------------------------------------------------
crc_trig_tx_wbs_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -833,8 +835,8 @@ begin
---------------------------------------------------------------------------
crc_data_rx_wbs_reg : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n,
......@@ -903,7 +905,7 @@ begin
----------------------------------------------------------------------------
-- STATUS Bus Implementation
----------------------------------------------------------------------------
stat_bus(511 downto 383) <= (OTHERS => '0');
stat_bus(511 downto 384) <= (OTHERS => '0');
stat_bus(299 downto 297) <= (OTHERS => '0');
stat_bus(187 downto 186) <= (OTHERS => '0');
stat_bus(98 downto 90) <= (OTHERS => '0');
......@@ -927,6 +929,9 @@ begin
stat_bus(STAT_IS_RECEIVER_INDEX) <=
is_receiver;
stat_bus(STAT_SOF_PULSE_INDEX) <=
sof_pulse_i;
stat_bus(STAT_PC_IS_ARBITRATION_INDEX) <=
is_arbitration;
......@@ -1149,10 +1154,10 @@ begin
bit_error;
stat_bus(STAT_BS_CTR_HIGH downto STAT_BS_CTR_LOW) <=
std_logic_vector(to_unsigned(bst_ctr, bst_ctr'length));
std_logic_vector(to_unsigned(bst_ctr, 3));
stat_bus(STAT_BD_CTR_HIGH downto STAT_BD_CTR_LOW) <=
std_logic_vector(to_unsigned(dst_ctr, bst_ctr'length));
std_logic_vector(to_unsigned(dst_ctr, 3));
stat_bus(STAT_TS_HIGH downto STAT_TS_LOW) <=
timestamp;
......@@ -1181,5 +1186,6 @@ begin
ssp_reset <= ssp_reset_i;
trv_delay_calib <= trv_delay_calib_i;
is_bus_off <= is_bus_off_i;
sof_pulse <= sof_pulse_i;
end architecture;
\ No newline at end of file
......@@ -72,7 +72,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -90,7 +89,7 @@ entity can_crc is
G_CRC17_POL : std_logic_vector(19 downto 0) := x"3685B";
-- CRC 15 polynomial
G_CRC21_POL : std_logic_vector(23 downto 0) := x"302899"
G_CRC21_POL : std_logic_vector(23 downto 0) := x"302899"
);
port(
------------------------------------------------------------------------
......
......@@ -64,7 +64,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -143,7 +142,7 @@ begin
----------------------------------------------------------------------------
crc_nxt <= data_in xor crc_reg(G_CRC_WIDTH - 1);
crc_shift <= crc_reg(crc_width - 2 downto 0) & '0';
crc_shift <= crc_reg(G_CRC_WIDTH - 2 downto 0) & '0';
crc_shift_n_xor <= crc_shift xor G_POLYNOMIAL(G_CRC_WIDTH - 1 downto 0);
......
......@@ -59,7 +59,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -224,9 +223,9 @@ begin
-- RX Error counter, next value calculation
----------------------------------------------------------------------------
-- Set to 120 when counter is more than 127, decrement otherwise!
rx_err_ctr_dec <= 120 when (rx_err_ctr_q > 127) else
(rx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else
rx_err_ctr_q;
rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else
(rx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else
rx_err_ctr_q;
-- Next value for error counter inctement when any of "inc" commands is
-- valid. Decrement otherwise!
......@@ -314,8 +313,8 @@ begin
rx_err_ctr <= std_logic_vector(rx_err_ctr_q);
tx_err_ctr <= std_logic_vector(tx_err_ctr_q);
norm_err_ctr <= nom_err_ctr_q;
data_err_ctr <= data_err_ctr_q;
norm_err_ctr <= std_logic_vector(nom_err_ctr_q);
data_err_ctr <= std_logic_vector(data_err_ctr_q);
----------------------------------------------------------------------------
-- Assertions
......@@ -335,12 +334,12 @@ begin
-- report "Unit can't be transmitter and receiver at once"
-- severity error;
-- psl rx_ctr_never_mt_262 : assert nevert
-- psl rx_ctr_never_mt_262 : assert never
-- (rx_err_ctr_q > 262)
-- report "RX Error counter is bigger than 262, node should be Bus off!"
-- severity error;
-- psl tx_ctr_never_mt_262 : assert nevert
-- psl tx_ctr_never_mt_262 : assert never
-- (tx_err_ctr_q > 262)
-- report "TX Error counter is bigger than 262, node should be Bus off!"
-- severity error;
......
......@@ -78,7 +78,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -187,8 +186,8 @@ architecture rtl of fault_confinement is
---------------------------------------------------------------------------
-- Driving bus aliases
---------------------------------------------------------------------------
signal drv_ewl : std_logic_vector(7 downto 0);
signal drv_erp : std_logic_vector(7 downto 0);
signal drv_ewl : std_logic_vector(8 downto 0);
signal drv_erp : std_logic_vector(8 downto 0);
signal drv_ctr_val : std_logic_vector(8 downto 0);
signal drv_ctr_sel : std_logic_vector(3 downto 0);
signal drv_clr_err_ctrs : std_logic;
......@@ -209,16 +208,16 @@ begin
---------------------------------------------------------------------------
-- Driving bus aliases
---------------------------------------------------------------------------
drv_ewl <= drv_bus(DRV_EWL_HIGH downto DRV_EWL_LOW);
drv_erp <= drv_bus(DRV_ERP_HIGH downto DRV_ERP_LOW);
drv_ewl <= '0' & drv_bus(DRV_EWL_HIGH downto DRV_EWL_LOW);
drv_erp <= '0' & drv_bus(DRV_ERP_HIGH downto DRV_ERP_LOW);
drv_ctr_val <= drv_bus(DRV_CTR_VAL_HIGH downto DRV_CTR_VAL_LOW);
drv_ctr_sel <= drv_bus(DRV_CTR_SEL_HIGH downto DRV_CTR_SEL_LOW);
drv_clr_err_ctrs <= drv_bus(DRV_ERR_CTR_CLR);
dff_arst_inst : dff_arst
generic map(
reset_polarity => G_RESET_POLARITY,
rst_val => '0'
G_RESET_POLARITY => G_RESET_POLARITY,
G_RST_VAL => '0'
)
port map(
arst => res_n, -- IN
......@@ -273,7 +272,7 @@ begin
reset_err_counters => set_err_active_q, -- IN
tx_err_ctr_pload => drv_ctr_sel(0), -- IN
rx_err_ctr_pload => drv_ctr_sel(1), -- IN
err_ctr_pload_val => drv_ctr_val, -- IN
drv_ctr_val => drv_ctr_val, -- IN
is_transmitter => is_transmitter, -- IN
is_receiver => is_receiver, -- IN
......
......@@ -58,7 +58,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -174,7 +173,7 @@ begin
when s_fc_bus_off =>
if (set_err_active = '1') then
next_state <= s_fc_err_active;
next_state <= s_fc_error_active;
end if;
end case;
......
......@@ -58,7 +58,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -67,7 +67,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......
......@@ -58,7 +58,6 @@ use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
......@@ -96,6 +95,9 @@ entity control_counter is
-- Pre-load value for control counter
ctrl_ctr_pload_val :in std_logic_vector(G_CTRL_CTR_WIDTH - 1 downto 0);
-- Complementary counter enable
compl_ctr_ena :in std_logic;
-----------------------------------------------------------------------
-- Status signals
......@@ -126,18 +128,22 @@ architecture rtl of control_counter is
-- Clock enable
signal ctrl_ctr_ce : std_logic;
-- Complementary register
signal compl_q : unsigned(G_CTRL_CTR_WIDTH - 1 downto 0);
-- Complementary register minus
signal ctrl_ctr_compl : unsigned(G_CTRL_CTR_WIDTH - 1 downto 0);
-- Complementary counter
signal compl_ctr_d : unsigned(G_CTRL_CTR_WIDTH - 1 downto 0);
signal compl_ctr_q : unsigned(G_CTRL_CTR_WIDTH - 1 downto 0);
signal compl_ctr_div_32 : unsigned(G_CTRL_CTR_WIDTH - 6 downto 0);
signal compl_ctr_div_32_plus_5 : integer range 0 to 21;
signal compl_ctr_ce : std_logic;