Commit 7d446960 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added Vivado benchmark project to evaluate FPGA resources.

parent 2d94b56b
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Apr 24 09:33:28 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="151929edaff848b780e40a893552cd2f" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="ReportTimingSummary" value="1" type="JavaHandler"/>
<property name="ResetLayout" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="2" type="JavaHandler"/>
<property name="RunSchematic" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="ShowPowerEstimation" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
<property name="ZoomIn" value="13" type="JavaHandler"/>
<property name="ZoomOut" value="7" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
<property name="ExpReportTreePanel_EXP_REPORT_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="14" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="39" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
<property name="GraphicalView_NEXT" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="6" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="6" type="GuiHandlerData"/>
<property name="NetlistSchematicView_SHOW_CELLS_IN_THIS_SCHEMATIC" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_IN" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="8" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="3" type="GuiHandlerData"/>
<property name="PrimitivesMenu_HIGHLIGHT_LEAF_CELLS" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_GROUP" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="3" type="GuiHandlerData"/>
<property name="SchematicView_PREVIOUS" value="10" type="GuiHandlerData"/>
<property name="SelectMenu_HIGHLIGHT" value="1" type="GuiHandlerData"/>
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_OPTIONS_TREE" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="5" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="SrcMenu_OPEN_SELECTED_SOURCE_FILES" value="1" type="GuiHandlerData"/>
<property name="XPowerSettingsDialog_CANCEL" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="5" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="3" type="TclMode"/>
</item>
</section>
</application>
</document>
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
reset_param project.defaultXPMLibraries
open_checkpoint /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/CAN_top_level.dcp
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CAN_top_level_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CAN_top_level_drc_opted.rpt -pb CAN_top_level_drc_opted.pb -rpx CAN_top_level_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
implement_debug_core
place_design
write_checkpoint -force CAN_top_level_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CAN_top_level_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CAN_top_level_utilization_placed.rpt -pb CAN_top_level_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CAN_top_level_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CAN_top_level_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CAN_top_level_drc_routed.rpt -pb CAN_top_level_drc_routed.pb -rpx CAN_top_level_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CAN_top_level_methodology_drc_routed.rpt -pb CAN_top_level_methodology_drc_routed.pb -rpx CAN_top_level_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CAN_top_level_power_routed.rpt -pb CAN_top_level_power_summary_routed.pb -rpx CAN_top_level_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CAN_top_level_route_status.rpt -pb CAN_top_level_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CAN_top_level_timing_summary_routed.rpt -warn_on_violation -rpx CAN_top_level_timing_summary_routed.rpx"
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CAN_top_level_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CAN_top_level_clock_utilization_routed.rpt"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CAN_top_level_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
#
vivado -log CAN_top_level.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CAN_top_level.tcl -notrace
#-----------------------------------------------------------
# Vivado v2017.3 (64-bit)
# SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
# IP Build 2016188 on Wed Oct 4 21:52:56 MDT 2017
# Start of session at: Thu Apr 19 18:30:37 2018
# Process ID: 28645
# Current directory: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1
# Command line: vivado -log CAN_top_level.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CAN_top_level.tcl -notrace
# Log file: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/CAN_top_level.vdi
# Journal file: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/vivado.jou
#-----------------------------------------------------------
source CAN_top_level.tcl -notrace
#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
create_project -in_memory -part xc7z007sclg225-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_vhdl -library xil_defaultlib {
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Libraries/CAN_FD_frame_format.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Libraries/CAN_FD_register_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Libraries/CANconstants.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Libraries/CANcomponents.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Registers_Memory_Interface/canfd_registers.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/rxBuffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/ID_transfer.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/txArbitrator.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/messageFilter.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Interrupts/intManager.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/operationControl.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/protocolControl.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/faultConf.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/CRC.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/bitStuffing_v2.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/bitDeStuffing.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/core_top.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Bus_Timing_Synchronisation/prescaler_v3.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Bus_Timing_Synchronisation/busSync.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/rst_sync.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Event_Logger/logger.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/priorityDecoder.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/txtBuffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_top_level.vhd
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
synth_design -top CAN_top_level -part xc7z007sclg225-2
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef CAN_top_level.dcp
create_report "synth_1_synth_report_utilization_0" "report_utilization -file CAN_top_level_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb"
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
| Date : Thu Apr 19 18:23:10 2018
| Host : ondrej-Aspire-V3-771 running 64-bit Ubuntu 16.04.4 LTS
| Command : report_utilization -file CAN_top_level_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb
| Design : CAN_top_level
| Device : 7z007sclg225-2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs* | 3126 | 0 | 14400 | 21.71 |
| LUT as Logic | 2930 | 0 | 14400 | 20.35 |
| LUT as Memory | 196 | 0 | 6000 | 3.27 |
| LUT as Distributed RAM | 196 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 1836 | 0 | 28800 | 6.38 |
| Register as Flip Flop | 1836 | 0 | 28800 | 6.38 |
| Register as Latch | 0 | 0 | 28800 | 0.00 |
| F7 Muxes | 44 | 0 | 8800 | 0.50 |
| F8 Muxes | 18 | 0 | 4400 | 0.41 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 199 | Yes | - | Set |
| 1618 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 19 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 2 | 0 | 50 | 4.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 4 | 0 | 100 | 4.00 |
| RAMB18E1 only | 4 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 66 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 161 | 0 | 54 | 298.15 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 54 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 54 | 0.00 |
| OLOGIC | 0 | 0 | 54 | 0.00 |
+-----------------------------+------+-------+-----------+--------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 8 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 1618 | Flop & Latch |
| LUT6 | 1418 | LUT |
| LUT2 | 774 | LUT |
| LUT4 | 610 | LUT |
| LUT5 | 424 | LUT |
| LUT3 | 424 | LUT |
| FDPE | 199 | Flop & Latch |
| RAMD32 | 130 | Distributed Memory |
| IBUF | 126 | IO |
| CARRY4 | 126 | CarryLogic |
| RAMD64E | 88 | Distributed Memory |
| MUXF7 | 44 | MuxFx |
| OBUF | 35 | IO |
| LUT1 | 32 | LUT |
| RAMS32 | 22 | Distributed Memory |
| FDRE | 19 | Flop & Latch |
| MUXF8 | 18 | MuxFx |
| RAMB18E1 | 4 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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