Commit 76766966 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '315-tx-arbitrator-extend-arbitration' into 'master'

Resolve "TX Arbitrator - extend arbitration"

Closes #315

See merge request !258
parents 44ed66ab f6d4399a
Pipeline #11382 passed with stage
in 16 seconds
This diff is collapsed.
......@@ -139,7 +139,10 @@ entity can_core is
-- TX Bit Rate Shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -482,6 +485,7 @@ begin
tran_ident_type => tran_ident_type, -- IN
tran_frame_type => tran_frame_type, -- IN
tran_brs => tran_brs, -- IN
tran_identifier => tran_identifier, -- IN
tran_frame_valid => tran_frame_valid, -- IN
txtb_hw_cmd => txtb_hw_cmd_i, -- IN
txtb_ptr => txtb_ptr, -- OUT
......
......@@ -165,6 +165,9 @@ entity protocol_control is
-- TX Bit rate shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -957,6 +960,7 @@ begin
is_err_active => is_err_active, -- IN
bst_ctr => bst_ctr, -- IN
tran_word => tran_word, -- IN
tran_identifier => tran_identifier, -- IN
tran_word_swapped => tran_word_swapped, -- IN
tran_dlc => tran_dlc -- IN
);
......
......@@ -158,6 +158,9 @@ entity tx_shift_reg is
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- TXT Buffer RAM word (byte endianity swapped)
tran_word_swapped :in std_logic_vector(31 downto 0);
......@@ -233,8 +236,8 @@ begin
stuff_count <= bst_ctr_grey & bst_parity;
-- Choosing Base and Ext IDs from TXT Buffer RAM memory words!
tx_base_id <= tran_word(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
tx_ext_id <= tran_word(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
tx_base_id <= tran_identifier(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L);
tx_ext_id <= tran_identifier(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L);
---------------------------------------------------------------------------
-- Shift register pre-load value:
......
......@@ -363,6 +363,9 @@ architecture rtl of can_top_level is
-- TX Frame Bit rate shift Flag
signal tran_brs : std_logic;
-- TX Identifier
signal tran_identifier : std_logic_vector(28 downto 0);
-- Word from TXT Buffer RAM selected by TX Arbitrator
signal tran_word : std_logic_vector(31 downto 0);
......@@ -651,6 +654,7 @@ begin
tran_ident_type => tran_ident_type, -- OUT
tran_frame_type => tran_frame_type, -- OUT
tran_brs => tran_brs, -- OUT
tran_identifier => tran_identifier, -- OUT
tran_frame_valid => tran_frame_valid, -- OUT
txtb_hw_cmd => txtb_hw_cmd, -- IN
txtb_changed => txtb_changed, -- OUT
......@@ -762,6 +766,7 @@ begin
tran_ident_type => tran_ident_type, -- IN
tran_frame_type => tran_frame_type, -- IN
tran_brs => tran_brs, -- IN
tran_identifier => tran_identifier, -- IN
tran_frame_valid => tran_frame_valid, -- IN
txtb_hw_cmd => txtb_hw_cmd, -- OUT
txtb_changed => txtb_changed, -- IN
......
......@@ -1917,7 +1917,10 @@ package can_components is
-- TX Bit rate shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -2442,6 +2445,9 @@ package can_components is
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- TXT Buffer RAM word (byte endianity swapped)
tran_word_swapped :in std_logic_vector(31 downto 0);
......@@ -2520,6 +2526,9 @@ package can_components is
-- TX Bit Rate Shift
tran_brs :in std_logic;
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
-- Frame in TXT Buffer is valid any can be transmitted.
tran_frame_valid :in std_logic;
......@@ -3941,7 +3950,7 @@ package can_components is
-- CAN Core Interface
-----------------------------------------------------------------------
-- HW Commands from CAN Core for manipulation with TXT Buffers
txtb_hw_cmd :in t_txtb_hw_cmd;
txtb_hw_cmd :in t_txtb_hw_cmd;
---------------------------------------------------------------------------
-- TX Arbitrator FSM outputs
......@@ -3954,13 +3963,22 @@ package can_components is
-- Load Frame format word to metadata pointer
load_ffmt_w_addr :out std_logic;
-- Load identifier word to metadata pointer
load_ident_w_addr :out std_logic;
-- Store timestamp lower word
store_ts_l_w :out std_logic;
-- Store metadata (Frame format word) on the output of TX Arbitrator
store_md_w :out std_logic;
-- Store identifier (Identifier word) on the output of TX Arbitrator
store_ident_w :out std_logic;
-- Store metadata (Frame format word) to double buffer registers.
buffer_md_w :out std_logic;
-- Signals that TX Arbitrator is locked (CAN Core is transmitting from TXT
-- Buffer)
tx_arb_locked :out std_logic;
......@@ -4027,7 +4045,10 @@ package can_components is
-- TX Frame Bit rate shift Flag
tran_brs :out std_logic;
-- TX Identifier
tran_identifier :out std_logic_vector(28 downto 0);
-- There is valid frame selected, can be locked for transmission
tran_frame_valid :out std_logic;
......
......@@ -141,9 +141,12 @@ package can_types is
-- TX arbitrator state type
type t_tx_arb_state is (
s_arb_idle,
s_arb_sel_low_ts,
s_arb_sel_upp_ts,
s_arb_sel_ffw,
s_arb_sel_idw,
s_arb_validated,
s_arb_locked
);
......
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......@@ -2464,7 +2464,8 @@ package body CANtestLib is
begin
if (id_type = EXTENDED) then
check(id_in < 536870912,
"Extended Identifier Exceeds the maximal value!");
"Extended Identifier: " & integer'image(id_in) &
" Exceeds the maximal value!");
id_vect := std_logic_vector(to_unsigned(id_in, 29));
id_out(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) :=
......@@ -2473,7 +2474,8 @@ package body CANtestLib is
id_vect(17 downto 0);
else
check(id_in < 2048,
"Base Identifier Exceeds the maximal value!");
"Base Identifier: " & integer'image(id_in) &
" Exceeds the maximal value!");
id_vect := "000000000000000000" &
std_logic_vector(to_unsigned(id_in, 11));
id_out(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) :=
......@@ -4665,15 +4667,17 @@ package body CANtestLib is
case data(ALC_ID_FIELD_H downto ALC_ID_FIELD_L) is
when ALC_BASE_ID =>
alc := 12 - to_integer(unsigned(data(ALC_BIT_H downto ALC_BIT_L)));
alc := 11 - to_integer(unsigned(data(ALC_BIT_H downto ALC_BIT_L)));
when ALC_EXTENSION =>
alc := 32 - to_integer(unsigned(data(ALC_BIT_H downto ALC_BIT_L)));
alc := 31 - to_integer(unsigned(data(ALC_BIT_H downto ALC_BIT_L)));
when ALC_SRR_RTR =>
alc := 12;
when ALC_IDE =>
alc := 13;
when ALC_RTR =>
alc := 33;
alc := 32;
when ALC_RSVD =>
alc := 0;
when others =>
error("Unsupported ALC type");
end case;
......
......@@ -44,7 +44,7 @@ feature:
timeout: 100 ms
wave: feature/feature_env_setup.tcl
tests:
arbitration:
alc_base_id:
mode_loopback:
mode_listen_only:
mode_self_test:
......
......@@ -70,7 +70,7 @@ feature:
timeout: 100 ms
wave: feature/feature_env_setup.tcl
tests:
arbitration:
alc_base_id:
mode_loopback:
iterations: 10
mode_listen_only:
......
......@@ -168,7 +168,8 @@ architecture Protocol_Control_unit_test of CAN_test is
signal tran_is_rtr_1 : std_logic;
signal tran_ident_type_1 : std_logic;
signal tran_frame_type_1 : std_logic;
signal tran_brs_1 : std_logic;
signal tran_brs_1 : std_logic;
signal tran_identifier_1 : std_logic_vector(28 downto 0);
signal tran_frame_valid_1 : std_logic;
signal txtb_hw_cmd_1 : t_txtb_hw_cmd;
signal txtb_ptr_1 : natural range 0 to 19;
......@@ -273,15 +274,20 @@ architecture Protocol_Control_unit_test of CAN_test is
signal is_overload_2 : std_logic;
-- TXT Buffers interface
signal tran_word_2 : std_logic_vector(31 downto 0);
signal tran_dlc_2 : std_logic_vector(3 downto 0);
signal tran_is_rtr_2 : std_logic;
signal tran_ident_type_2 : std_logic;
signal tran_frame_type_2 : std_logic;
signal tran_brs_2 : std_logic;
signal tran_frame_valid_2 : std_logic;
signal txtb_hw_cmd_2 : t_txtb_hw_cmd;
signal txtb_ptr_2 : natural range 0 to 19;
signal tran_word_2 : std_logic_vector(31 downto 0)
:= (OTHERS => '0');
signal tran_dlc_2 : std_logic_vector(3 downto 0)
:= (OTHERS => '0');
signal tran_is_rtr_2 : std_logic := '0';
signal tran_ident_type_2 : std_logic := '0';
signal tran_frame_type_2 : std_logic := '0';
signal tran_brs_2 : std_logic := '0';
signal tran_identifier_2 : std_logic_vector(28 downto 0) := (OTHERS => '0');
signal tran_frame_valid_2 : std_logic := '0';
signal txtb_hw_cmd_2 : t_txtb_hw_cmd;
signal txtb_ptr_2 : natural range 0 to 19;
signal txtb_changed_2 : std_logic := '0';
-- RX Buffer interface
......@@ -676,6 +682,7 @@ begin
tran_ident_type => tran_ident_type_1,
tran_frame_type => tran_frame_type_1,
tran_brs => tran_brs_1,
tran_identifier => tran_identifier_1,
tran_frame_valid => tran_frame_valid_1,
txtb_hw_cmd => txtb_hw_cmd_1,
txtb_ptr => txtb_ptr_1,
......@@ -798,6 +805,7 @@ begin
tran_ident_type => tran_ident_type_2,
tran_frame_type => tran_frame_type_2,
tran_brs => tran_brs_2,
tran_identifier => tran_identifier_2,
tran_frame_valid => tran_frame_valid_2,
txtb_hw_cmd => txtb_hw_cmd_2,
txtb_ptr => txtb_ptr_2,
......@@ -960,6 +968,7 @@ begin
begin
wait until rising_edge(clk_sys);
tran_word_1 <= txtb_mem(txtb_ptr_1);
tran_identifier_1 <= txtb_mem(1)(28 downto 0);
end process;
......
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