Commit 608a2032 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added optional byte enable support.

parent 40b54e63
......@@ -98,6 +98,7 @@ entity CAN_top_level is
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant tx_time_sup : boolean := true;
constant sup_be : boolean := true;
constant logger_size : natural range 0 to 512 := 8
);
port(
......@@ -478,6 +479,7 @@ begin
sup_filtB => sup_filtB,
sup_filtC => sup_filtC,
sup_range => sup_range,
sup_be => sup_be,
ID => ID
)
port map(
......
......@@ -74,6 +74,7 @@ package CANcomponents is
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant tx_time_sup : boolean := true;
constant sup_be : boolean := false;
constant logger_size : natural --range 0 to 512:=8
);
port(
......@@ -112,6 +113,7 @@ package CANcomponents is
constant sup_filtB : boolean := true;
constant sup_filtC : boolean := true;
constant sup_range : boolean := true;
constant sup_be : boolean := false;
constant ID : natural
);
port(
......
......@@ -120,6 +120,9 @@ entity canfd_registers is
constant sup_filtC :boolean := true;
constant sup_range :boolean := true;
--Support of byte enable signal on memory bus interface
constant sup_be :boolean := false;
--ID of the component
constant ID :natural := 1
);
......@@ -525,13 +528,17 @@ architecture rtl of canfd_registers is
signal be : in std_logic_vector(3 downto 0)
)is
begin
if (bit_index<8 and be(0)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<16 and bit_index>7 and be(1)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<24 and bit_index>15 and be(2)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<32 and bit_index>23 and be(3)='1') then
if (sup_be = true) then
if (bit_index<8 and be(0)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<16 and bit_index>7 and be(1)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<24 and bit_index>15 and be(2)='1') then
dest_reg := data_in(bit_index);
elsif (bit_index<32 and bit_index>23 and be(3)='1') then
dest_reg := data_in(bit_index);
end if;
else
dest_reg := data_in(bit_index);
end if;
end procedure;
......@@ -547,13 +554,17 @@ architecture rtl of canfd_registers is
signal be : in std_logic_vector(3 downto 0)
)is
begin
if (bit_index<8 and be(0)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<16 and bit_index>7 and be(1)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<24 and bit_index>15 and be(2)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<32 and bit_index>23 and be(3)='1') then
if (sup_be = true) then
if (bit_index<8 and be(0)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<16 and bit_index>7 and be(1)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<24 and bit_index>15 and be(2)='1') then
dest_reg <= data_in(bit_index);
elsif (bit_index<32 and bit_index>23 and be(3)='1') then
dest_reg <= data_in(bit_index);
end if;
else
dest_reg <= data_in(bit_index);
end if;
end procedure;
......
......@@ -60,7 +60,8 @@ entity CAN_Wrapper is
constant sup_filtB : boolean:= true;
constant sup_filtC : boolean:= true;
constant sup_range : boolean:= true;
constant tx_time_sup : boolean:= true;
constant tx_time_sup : boolean:= true;
constant sup_be : boolean:= false;
constant logger_size : natural:= 8
);
port (
......@@ -212,6 +213,7 @@ begin
sup_filtC => sup_filtC,
sup_range => sup_range,
tx_time_sup => tx_time_sup,
sup_be => sup_be,
logger_size => logger_size
)
port map(
......
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