Commit 4e7819e1 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge remote-tracking branch 'origin/master' into 210-prescaler-fsm-rework

# Conflicts:
#	doc/core/Progdokum.lyx
parents c4b464ff 15cb820e
......@@ -506,12 +506,6 @@ CTU CAN FD IP Core
\begin_inset Text
\begin_layout Plain Layout
\begin_inset CommandInset include
LatexCommand input
filename "version.tex"
\end_inset
\end_layout
......@@ -881,7 +875,7 @@ Ondrej Ille
\begin_inset Text
\begin_layout Plain Layout
Re-worked Prescaler.
Re-worked Prescaler. Removed 0x3 in bits 23:20 of address.
\end_layout
\end_inset
......@@ -1981,10 +1975,6 @@ ID
With this architecture, it is possible to create up to 16 instances on
a single parallel memory bus.
More cores can be instantiated when using Interconnect components.
Address bits 23:20 must have constant value 0x3.
This requirement is given by a custom system for which this core was originally
developed.
Description of this system is beyond the scope of this document.
\end_layout
\begin_layout Standard
......@@ -1997,26 +1987,16 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="2" columns="3">
<lyxtabular version="3" rows="2" columns="2">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 23:20
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 19:16
Avalon Address 15:12
\end_layout
\end_inset
......@@ -2025,7 +2005,7 @@ Avalon Address 19:16
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 15:0
Avalon Address 11:0
\end_layout
\end_inset
......@@ -2035,15 +2015,6 @@ Avalon Address 15:0
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0x3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\family roman
......@@ -2677,7 +2648,7 @@ in
\begin_inset Text
\begin_layout Plain Layout
24
16
\end_layout
\end_inset
......
Subproject commit d0d572b431887051295461eb5aa2c78736f7b10a
Subproject commit 4e78535d62f76ae5a0b91819ab6cbb914cba4662
......@@ -81,7 +81,7 @@ entity apb_ifc is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......@@ -119,9 +119,6 @@ begin
reg_data_in_o <= s_apb_pwdata;
s_apb_prdata <= reg_data_out_i;
reg_addr_o(COMP_TYPE_ADRESS_HIGHER downto COMP_TYPE_ADRESS_LOWER) <=
CAN_COMPONENT_TYPE;
reg_addr_o(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) <=
std_logic_vector(to_unsigned(ID, 4));
......
......@@ -523,26 +523,6 @@ architecture rtl of can_core is
-- Signals start of frame to rest of the design
signal sof_pulse_r : std_logic;
for operation_control_comp : operation_control
use entity work.operation_control(rtl);
for protocol_control_comp : protocol_control
use entity work.protocol_control(rtl);
for fault_confinement_comp : fault_confinement
use entity work.fault_confinement(rtl);
for crc_wrapper_comp : crc_wrapper
use entity work.crc_wrapper(rtl);
for bit_stuffing_comp : bit_stuffing
use entity work.bit_stuffing(rtl);
for bit_destuffing_comp : bit_destuffing
use entity work.bit_destuffing(rtl);
begin
-- Internal signals to output propagation
......
......@@ -104,7 +104,7 @@ architecture rtl of CTU_CAN_FD_v1_0 is
signal reg_data_in : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(23 downto 0);
signal reg_addr : std_logic_vector(15 downto 0);
signal reg_be : std_logic_vector(3 downto 0);
signal reg_rden : std_logic;
signal reg_wren : std_logic;
......
......@@ -73,6 +73,7 @@
-- anymore.
-- 15.2.2018 Added generic amount of TXT Buffers and support for TXT
-- buffer FSM, HW commands and SW commands.
-- 18.3.2019 Remove explicit architecture assignments.
--------------------------------------------------------------------------------
Library ieee;
......@@ -129,7 +130,7 @@ entity can_top_level is
---------------------
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
......@@ -477,20 +478,6 @@ architecture rtl of CAN_top_level is
-- Transceiver delay output
signal trv_delay_out : std_logic_vector(15 downto 0);
----------------------------------------------------------------------------
-- Defining explicit architectures for used entites
----------------------------------------------------------------------------
for memory_registers_comp : memory_registers use entity work.memory_registers(rtl);
for rx_buffer_comp : rx_buffer use entity work.rx_buffer(rtl);
for tx_arbitrator_comp : tx_arbitrator use entity work.tx_arbitrator(rtl);
for frame_filters_comp : frame_filters use entity work.frame_filters(rtl);
for int_manager_comp : int_manager use entity work.int_manager(rtl);
for can_core_comp : can_core use entity work.can_core(rtl);
for prescaler_comp : prescaler use entity work.prescaler(rtl);
for bus_sampling_comp : bus_sampling use entity work.bus_sampling(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
begin
-- synthesis translate_off
......@@ -510,7 +497,6 @@ begin
memory_registers_comp : memory_registers
generic map(
compType => CAN_COMPONENT_TYPE,
use_logger => use_logger,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
......
......@@ -86,7 +86,7 @@ package can_components is
signal res_n : in std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -116,7 +116,6 @@ package can_components is
----------------------------------------------------------------------------
component memory_registers is
generic(
constant compType : std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
constant use_logger : boolean := true;
constant sup_filtA : boolean := true;
constant sup_filtB : boolean := true;
......@@ -135,7 +134,7 @@ package can_components is
signal res_out : out std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -1337,7 +1336,7 @@ package can_components is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......
......@@ -154,30 +154,13 @@ package can_constants is
----------------------------------------------------------------------------
-- Memory Access
----------------------------------------------------------------------------
-- General Purpose register
constant GPR_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"1";
-- OutPut Multiplexor component type
constant OUTMUX_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"2";
-- FlexRay Node
constant FLEXRAY_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"3";
-- CAN Node
constant CAN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"4";
-- LIN Node
constant LIN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"5";
constant ACT_CSC : std_logic := '1';
constant ACT_SRD : std_logic := '1';
constant ACT_SWR : std_logic := '1';
-- Address ranges for component type and identifier
constant COMP_TYPE_ADRESS_HIGHER : natural := 23;
constant COMP_TYPE_ADRESS_LOWER : natural := 20;
constant ID_ADRESS_HIGHER : natural := 19;
constant ID_ADRESS_LOWER : natural := 16;
-- Address ranges for identifier
constant ID_ADRESS_HIGHER : natural := 15;
constant ID_ADRESS_LOWER : natural := 12;
constant CAN_DEVICE_ID : std_logic_vector(31 downto 0) := x"0000CAFD";
......
......@@ -49,6 +49,25 @@ use ieee.std_logic_1164.all;
package can_fd_frame_format is
------------------------------------------------------------------------------
-- Common types
------------------------------------------------------------------------------
type t_reg_type is (
reg_none,
reg_write_only,
reg_read_only,
reg_read_write,
reg_read_write_once
);
type t_reg is record
address : std_logic_vector(11 downto 0);
size : integer;
reg_type : t_reg_type;
reset_val : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Address block: CAN_FD_Frame_format
......@@ -64,6 +83,44 @@ package can_fd_frame_format is
constant DATA_5_8_W_ADR : std_logic_vector(11 downto 0) := x"014";
constant DATA_61_64_W_ADR : std_logic_vector(11 downto 0) := x"04C";
------------------------------------------------------------------------------
-- Register list
------------------------------------------------------------------------------
type t_CAN_FD_Frame_format_list is array (0 to 6) of t_reg;
constant CAN_FD_Frame_format_list : t_CAN_FD_Frame_format_list :=(
(address => FRAME_FORM_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => IDENTIFIER_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => TIMESTAMP_L_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => TIMESTAMP_U_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => DATA_1_4_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => DATA_5_8_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000"),
(address => DATA_61_64_W_ADR,
size => 32,
reg_type => reg_none,
reset_val => "00000000000000000000000000000000")
);
------------------------------------------------------------------------------
-- FRAME_FORM_W register
--
......
This diff is collapsed.
......@@ -148,8 +148,6 @@ use work.can_registers_pkg.all;
entity memory_registers is
generic(
constant compType :std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
-- Whenever event logger is present
constant use_logger :boolean := true;
......@@ -190,7 +188,7 @@ entity memory_registers is
------------------------------------------------------------------------
signal data_in :in std_logic_vector(31 downto 0);
signal data_out :out std_logic_vector(31 downto 0);
signal adress :in std_logic_vector(23 downto 0);
signal adress :in std_logic_vector(15 downto 0);
signal scs :in std_logic;
signal srd :in std_logic;
signal swr :in std_logic;
......@@ -392,8 +390,6 @@ begin
end generate txtb_cs_gen;
can_core_cs <= '1' when (scs = ACT_CSC) and
(adress(COMP_TYPE_ADRESS_HIGHER downto
COMP_TYPE_ADRESS_LOWER) = compType) and
(adress(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) =
std_logic_vector(to_unsigned(ID, 4)))
else
......@@ -446,7 +442,7 @@ begin
control_registers_reg_map_comp : control_registers_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
REGISTERED_READ => true,
CLEAR_READ_DATA => true,
RESET_POLARITY => ACT_RESET,
......@@ -480,7 +476,7 @@ begin
event_logger_reg_map_comp : event_logger_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
CLEAR_READ_DATA => true,
REGISTERED_READ => true,
RESET_POLARITY => ACT_RESET
......
......@@ -120,7 +120,7 @@ architecture feature_env_test of CAN_feature_test is
data_in : std_logic_vector(31 downto 0);
data_out : std_logic_vector(31 downto 0);
adress : std_logic_vector(23 downto 0);
adress : std_logic_vector(15 downto 0);
scs : std_logic; --Chip select
srd : std_logic; --Serial read
swr : std_logic; --Serial write
......@@ -194,7 +194,7 @@ begin
-------------------------------------------------
x1: mem_bus(i).clk_sys <= p(i).clk_sys;
x2: p(i).data_in <= mem_bus(i).data_in;
x3: p(i).adress <= mem_bus(i).address;
x3: p(i).adress <= mem_bus(i).address(15 downto 0);
x4: p(i).scs <= mem_bus(i).scs;
x5: p(i).swr <= mem_bus(i).swr;
x6: p(i).srd <= mem_bus(i).srd;
......
This diff is collapsed.
......@@ -69,5 +69,3 @@ add wave -label "CAN RX" $TCOMP/can_rx
add wave -noupdate -divider -height 20 "CAN Node"
add wave -label "Protocol control" $TCOMP/CAN_inst/can_core_comp/PC_State
add wave -label "Bit timing state" $TCOMP/CAN_inst/bt_FSM_out
......@@ -69,7 +69,7 @@ architecture CAN_reference_test of CAN_test is
signal timestamp : std_logic_vector(63 downto 0) := (OTHERS => '0');
signal data_in : std_logic_vector(31 downto 0) := (OTHERS => '0');
signal data_out : std_logic_vector(31 downto 0);
signal adress : std_logic_vector(23 downto 0) := (OTHERS => '0');
signal adress : std_logic_vector(15 downto 0) := (OTHERS => '0');
signal scs : std_logic := '0';
signal srd : std_logic := '0';
signal swr : std_logic := '0';
......@@ -304,7 +304,7 @@ begin
scs <= mem_bus.scs;
srd <= mem_bus.srd;
swr <= mem_bus.swr;
adress <= mem_bus.address;
adress <= mem_bus.address(15 downto 0);
data_in <= mem_bus.data_in;
mem_bus.data_out <= data_out;
......
......@@ -158,7 +158,7 @@ architecture behavioral of sanity_test is
array (1 to NODE_COUNT) of std_logic_vector(3 downto 0);
type mem_addr_arr_type is
array (1 to NODE_COUNT) of std_logic_vector(23 downto 0);
array (1 to NODE_COUNT) of std_logic_vector(15 downto 0);
signal mem_aux_data_in : mem_vect_arr_type :=
(OTHERS => (OTHERS => '0'));
......@@ -485,7 +485,7 @@ begin
mb_arr(i).clk_sys <= mem_aux_clk(i);
mem_aux_data_in(i) <= mb_arr(i).data_in;
mem_aux_address(i) <= mb_arr(i).address;
mem_aux_address(i) <= mb_arr(i).address(15 downto 0);
mem_aux_scs(i) <= mb_arr(i).scs;
mem_aux_swr(i) <= mb_arr(i).swr;
mem_aux_srd(i) <= mb_arr(i).srd;
......
......@@ -71,15 +71,19 @@ def create():
pass
# NOTE: I'd like to use [True, False, None] for strict, but click is damn
# stubborn about interpreting None as False
@cli.command()
@click.argument('config', type=click.Path())
@click.argument('vunit_args', nargs=-1)
@click.option('--strict/--no-strict', default=True,
@click.option('--__strict-from-config', 'strict', flag_value=-1, default=True, hidden=True)
@click.option('--strict', 'strict', flag_value=1,
help='Return non-zero if an unconfigured test was found.')
@click.option('--no-strict', 'strict', flag_value=0)
@click.option('--create-ghws/--no-create-ghws', default=False,
help='Only elaborate and create basic GHW files necessary for converting TCL layout files to GTKW files for gtkwave..')
@click.pass_obj
def test(obj, config, strict, create_ghws, vunit_args):
def test(obj, *, config, strict, create_ghws, vunit_args):
"""Run the tests. Configuration is passed in YAML config file.
You mas pass arguments directly to VUnit by appending them at the command end.
......@@ -110,9 +114,18 @@ def test(obj, config, strict, create_ghws, vunit_args):
build.mkdir(exist_ok=True)
os.chdir(str(build))
if 'strict' in config:
if strict == -1:
strict = config['strict']
if strict == -1:
strict = 0
strict = bool(strict)
if create_ghws:
# discard the passed vunit_args, it does only evil
vunit_args = ['--elaborate']
# filter out "-g" (gui mode) - it causes problems.
# It's not 100% fool-proof, but should catch 99% of cases.
vunit_args = [a for a in vunit_args if a != '-g']
vunit_args += ['--elaborate']
ui = create_vunit(obj, vunit_args, out_basename)
......
......@@ -56,6 +56,7 @@ def factory(line: str):
'port-in': signal.create,
'port-out': signal.create,
'port-inout': signal.create,
'port-buffer': signal.create,
'generate-for': generate_for.create,
'package': container.create,
'process': container.create,
......
......@@ -134,9 +134,9 @@ def add_flags(ui, lib, build) -> None:
rt.scan_tests_from_file(str(build / "../reference/vunit_reference_wrapper.vhd"))
#lib.add_compile_option("ghdl.flags", ["-Wc,-g"])
lib.add_compile_option("ghdl.flags", ["-fprofile-arcs", "-ftest-coverage", "-fpsl"])
lib.add_compile_option("ghdl.flags", ["-fprofile-arcs", "-ftest-coverage", "-fpsl", "-g"])
elab_flags = ["-Wl,-lgcov"]
elab_flags = ["-Wl,-lgcov", "-g"]
elab_flags.append("-Wl,--coverage")
elab_flags.append("-Wl,-no-pie")
elab_flags.append("-fpsl")
......
......@@ -26,19 +26,18 @@ class ReferenceTests(TestsBase):
def configure(self) -> bool:
tb = self.lib.get_test_benches('*reference*')[0]
default = self.config['default']
self.add_modelsim_gui_file(tb, default, 'sanity')
tcl = self.build / 'modelsim_init_reference.tcl'
with tcl.open('wt', encoding='utf-8') as f:
print(dedent('''\
global TCOMP
set TCOMP i_test
set TCOMP tb_reference_wrapper/i_test
'''), file=f)
init_files = get_common_modelsim_init_files()
init_files += [str(tcl)]
for data_set,cfg in self.config['tests'].items():
for data_set, cfg in self.config['tests'].items():
dict_merge(cfg, default)
# bm = len_to_matrix(cfg['topology'], cfg['bus_len_v'])
generics = {
......@@ -56,6 +55,6 @@ class ReferenceTests(TestsBase):
else:
tb.add_config(data_set, generics=generics)
tb.set_sim_option("modelsim.init_files.after_load", init_files)
self.add_modelsim_gui_file(tb, cfg, data_set, init_files)
tb.set_sim_option("modelsim.init_files.after_load", init_files)
self.add_modelsim_gui_file(tb, default, 'reference', init_files)
return True
......@@ -96,7 +96,7 @@ class SanityTests(TestsBase):
sanity_cfg_name = name.replace(" ", "_").replace("/", "_").strip('"')
if (cfg['psl_coverage']):
if cfg['psl_coverage']:
psl_opts = self.create_psl_cov_file_opt(name)
tb.add_config(name, generics=generics, sim_options=psl_opts)
else:
......
strict: false # unconfigured tests reported as error; defaults to true
_default: &default
log_level: info
error_tolerance: 0
......
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