Commit 3b6cbe45 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Removed duplicate driver for higher bits of LOG_STATUS register.

parent 1e2ac22c
Pipeline #5595 passed with stages
in 11 minutes and 4 seconds
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......@@ -1659,7 +1659,6 @@ begin
log_size;
-- Pad unused by zeroes
Event_Logger_in.log_status(15 downto 8) <= (OTHERS => '0');
Event_Logger_in.log_status(6 downto 3) <= (OTHERS => '0');
end block log_status_block;
......
......@@ -3,7 +3,7 @@
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The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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......@@ -17,49 +17,50 @@ This means code written to parse this file will need to be revisited each subseq
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......@@ -78,25 +79,27 @@ This means code written to parse this file will need to be revisited each subseq
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......@@ -105,23 +108,24 @@ This means code written to parse this file will need to be revisited each subseq
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......@@ -134,19 +138,23 @@ This means code written to parse this file will need to be revisited each subseq
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......@@ -157,7 +165,7 @@ This means code written to parse this file will need to be revisited each subseq
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......
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</Runs>
#
# Synthesis run script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
create_project -in_memory -part xc7z007sclg225-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property default_lib lib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
set_property generic {dummy=Minimal_configuration use_logger=false rx_buffer_size=32 use_sync=true ID=1 sup_filtA=false sup_filtB=false sup_filtC=false sup_range=false logger_size=8} [current_fileset]
read_vhdl -vhdl2008 -library lib {
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_fd_frame_format.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_clean/src/ID_transfer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/access_signaler.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/address_decoder.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/id_transfer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_constants.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_types.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/can_registers_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_clean/src/Registers_Memory_Interface/generated/can_registers_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_components.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/cmn_lib.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/drv_stat_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/endian_swap.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_clean/src/endian_swap.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/reduce_lib.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/can_fd_register_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/lib/synth_context.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/apb/apb_ifc.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bit_destuffing/bit_destuffing.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/bit_filter.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bit_stuffing/bit_stuffing.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/bus_sampling/bus_sampling.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/bus_traffic_counters/bus_traffic_counters.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/operation_control/operation_control.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/protocol_control/protocol_control.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/fault_confinement/fault_confinement.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/crc_wrapper.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/can_core.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/can_crc.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/memory_registers.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/tx_arbitrator.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/frame_filters.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/interrupts/int_manager.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/prescaler/prescaler.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/rst_sync.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_top_level.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/cmn_reg_map_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_clean/src/Registers_Memory_Interface/generated/cmn_reg_map_pkg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/control_registers_reg_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_core/crc/crc_calc.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/data_mux.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/dff_arst.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/event_logger/event_logger.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/event_logger_reg_map.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/inf_ram_wrapper.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/interrupts/int_module.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/majority_decoder_3.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/memory_registers/generated/memory_reg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/priority_decoder.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/frame_filters/range_filter.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/rx_buffer/rx_buffer_pointers.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/shift_reg.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/shift_reg_preload.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/common/sig_sync.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/tx_arbitrator/tx_arbitrator_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/txt_buffer/txt_buffer.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/txt_buffer/txt_buffer_fsm.vhd
/DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/src/can_top_apb.vhd
}
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc
set_property used_in_implementation false [get_files /DOKUMENTY/Skola/CVUT-FEL/ctu_can_fd_2/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc]
synth_design -top CTU_CAN_FD_v1_0 -part xc7z007sclg225-2 -flatten_hierarchy none -retiming
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef CTU_CAN_FD_v1_0.dcp
create_report "Benchmark:Minimal_configuration_synth_report_utilization_0" "report_utilization -file CTU_CAN_FD_v1_0_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb"
This source diff could not be displayed because it is too large. You can view the blob instead.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
| Date : Sat Dec 29 15:43:41 2018
| Host : ondrej-Aspire-V3-771 running 64-bit Ubuntu 18.04.1 LTS
| Command : report_utilization -file CTU_CAN_FD_v1_0_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb
| Design : CTU_CAN_FD_v1_0
| Device : 7z007sclg225-2
| Design State : Synthesized
-----------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 2397 | 0 | 14400 | 16.65 |
| LUT as Logic | 2397 | 0 | 14400 | 16.65 |
| LUT as Memory | 0 | 0 | 6000 | 0.00 |
| Slice Registers | 1495 | 0 | 28800 | 5.19 |
| Register as Flip Flop | 1495 | 0 | 28800 | 5.19 |
| Register as Latch | 0 | 0 | 28800 | 0.00 |
| F7 Muxes | 66 | 0 | 8800 | 0.75 |
| F8 Muxes | 18 | 0 | 4400 | 0.41 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 193 | Yes | - | Set |
| 1290 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 12 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 2.5 | 0 | 50 | 5.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 5 | 0 | 100 | 5.00 |
| RAMB18E1 only | 5 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 66 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 153 | 0 | 54 | 283.33 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |