Commit 3074f22c authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Accustomize TB to removal of hardcoded address.

parent e00cf5c4
......@@ -120,7 +120,7 @@ architecture feature_env_test of CAN_feature_test is
data_in : std_logic_vector(31 downto 0);
data_out : std_logic_vector(31 downto 0);
adress : std_logic_vector(23 downto 0);
adress : std_logic_vector(15 downto 0);
scs : std_logic; --Chip select
srd : std_logic; --Serial read
swr : std_logic; --Serial write
......@@ -194,7 +194,7 @@ begin
-------------------------------------------------
x1: mem_bus(i).clk_sys <= p(i).clk_sys;
x2: p(i).data_in <= mem_bus(i).data_in;
x3: p(i).adress <= mem_bus(i).address;
x3: p(i).adress <= mem_bus(i).address(15 downto 0);
x4: p(i).scs <= mem_bus(i).scs;
x5: p(i).swr <= mem_bus(i).swr;
x6: p(i).srd <= mem_bus(i).srd;
......
This diff is collapsed.
......@@ -69,7 +69,7 @@ architecture CAN_reference_test of CAN_test is
signal timestamp : std_logic_vector(63 downto 0) := (OTHERS => '0');
signal data_in : std_logic_vector(31 downto 0) := (OTHERS => '0');
signal data_out : std_logic_vector(31 downto 0);
signal adress : std_logic_vector(23 downto 0) := (OTHERS => '0');
signal adress : std_logic_vector(15 downto 0) := (OTHERS => '0');
signal scs : std_logic := '0';
signal srd : std_logic := '0';
signal swr : std_logic := '0';
......@@ -304,7 +304,7 @@ begin
scs <= mem_bus.scs;
srd <= mem_bus.srd;
swr <= mem_bus.swr;
adress <= mem_bus.address;
adress <= mem_bus.address(15 downto 0);
data_in <= mem_bus.data_in;
mem_bus.data_out <= data_out;
......
......@@ -158,7 +158,7 @@ architecture behavioral of sanity_test is
array (1 to NODE_COUNT) of std_logic_vector(3 downto 0);
type mem_addr_arr_type is
array (1 to NODE_COUNT) of std_logic_vector(23 downto 0);
array (1 to NODE_COUNT) of std_logic_vector(15 downto 0);
signal mem_aux_data_in : mem_vect_arr_type :=
(OTHERS => (OTHERS => '0'));
......@@ -485,7 +485,7 @@ begin
mb_arr(i).clk_sys <= mem_aux_clk(i);
mem_aux_data_in(i) <= mb_arr(i).data_in;
mem_aux_address(i) <= mb_arr(i).address;
mem_aux_address(i) <= mb_arr(i).address(15 downto 0);
mem_aux_scs(i) <= mb_arr(i).scs;
mem_aux_swr(i) <= mb_arr(i).swr;
mem_aux_srd(i) <= mb_arr(i).srd;
......
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