Commit 27d09104 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '210-prescaler-fsm-rework' into 'master'

Resolve "Prescaler FSM rework"

Closes #210

See merge request !242
parents 15cb820e 087c605b
Pipeline #6833 passed with stage
in 47 seconds
This diff is collapsed.
......@@ -255,7 +255,10 @@ entity can_core is
-- trigger signal therefore logically belongs here
-- Synchronisation control signal (Hard sync, Re Sync)
signal sync_control :out std_logic_vector(1 downto 0);
signal sync_control :out std_logic_vector(1 downto 0);
-- No positive resynchronisation
signal no_pos_resync :out std_logic;
------------------------------------------------------------------------
-- Recieve and transcieved data interface
......@@ -983,6 +986,15 @@ begin
drv_int_loopback_ena = '1')
else
data_tx_from_PC;
----------------------------------------------------------------------------
-- No positive resynchronisation for transceiver due to RECESSIVE to
-- DOMINANT transition.
----------------------------------------------------------------------------
no_pos_resync <= '1' when (OP_State = transciever and data_tx = DOMINANT)
else
'0';
----------------------------------------------------------------------------
......
......@@ -2446,7 +2446,7 @@ begin
-- frame otherwise. If sampled
--------------------------------------------------------
when 0 =>
if (ack_recieved = '1' and data_rx = RECESSIVE) then
if (ack_recieved = '1') then
PC_State <= eof;
else
PC_State <= error;
......
......@@ -412,13 +412,7 @@ architecture rtl of CAN_top_level is
--Protocol control state
signal OP_State : oper_mode_type;
--Time quantum clock - Nominal bit time
signal clk_tq_nbt : std_logic;
--Bit time - Nominal bit time
signal clk_tq_dbt : std_logic;
--Sample signal for nominal bit time
signal sample_nbt : std_logic;
......@@ -437,17 +431,21 @@ architecture rtl of CAN_top_level is
signal sync_nbt_del_1 : std_logic;
signal sync_dbt_del_1 : std_logic;
-- Trigger outputs from Prescaler
signal sample_nbt_i : std_logic_vector(2 downto 0);
signal sample_dbt_i : std_logic_vector(2 downto 0);
signal sync_nbt_i : std_logic_vector(1 downto 0);
signal sync_dbt_i : std_logic_vector(1 downto 0);
signal sp_control : std_logic_vector(1 downto 0);
signal sync_control : std_logic_vector(1 downto 0);
signal bt_FSM_out : bit_time_type;
--Validated hard synchronisation edge to start Protocol control FSM
-- Validated hard synchronisation edge to start Protocol control FSM
signal hard_sync_edge_valid : std_logic;
--Note: Sync edge from busSync.vhd cant be used! If it comes during sample
-- nbt, sequence it causes errors! It needs to be strictly before or
-- strictly after this sequence!!!
signal no_pos_resync : std_logic;
----------------------------------------------------------------------------
-- Bus Synchroniser Interface
......@@ -750,6 +748,7 @@ begin
sample_sec_del_1 => sample_sec_del_1,
sample_sec_del_2 => sample_sec_del_2,
sync_control => sync_control,
no_pos_resync => no_pos_resync,
data_rx => data_rx,
data_tx => data_tx,
timestamp => timestamp,
......@@ -763,30 +762,57 @@ begin
);
prescaler_comp : prescaler
generic map(
reset_polarity => ACT_RESET,
capt_btr => false,
capt_tseg_1 => true,
capt_tseg_2 => false,
capt_sjw => false,
-- Width of Bit time segments
tseg1_nbt_width => 8,
tseg2_nbt_width => 6,
tq_nbt_width => 8,
sjw_nbt_width => 5,
tseg1_dbt_width => 7,
tseg2_dbt_width => 5,
tq_dbt_width => 8,
sjw_dbt_width => 5,
sync_trigger_count => 2,
sample_trigger_count => 3
)
port map(
clk_sys => clk_sys,
res_n => res_n_int,
OP_State => OP_State,
sync_edge => sync_edge,
drv_bus => drv_bus,
clk_tq_nbt => clk_tq_nbt,
clk_tq_dbt => clk_tq_dbt,
sample_nbt => sample_nbt,
sample_dbt => sample_dbt,
sample_nbt => sample_nbt_i,
sample_dbt => sample_dbt_i,
bt_FSM_out => bt_FSM_out,
sample_nbt_del_1 => sample_nbt_del_1,
sample_dbt_del_1 => sample_dbt_del_1,
sample_nbt_del_2 => sample_nbt_del_2,
sample_dbt_del_2 => sample_dbt_del_2,
sync_nbt => sync_nbt,
sync_dbt => sync_dbt,
sync_nbt_del_1 => sync_nbt_del_1,
sync_dbt_del_1 => sync_dbt_del_1,
data_tx => data_tx,
sync_nbt => sync_nbt_i,
sync_dbt => sync_dbt_i,
time_quanta_clk => time_quanta_clk,
hard_sync_edge_valid => hard_sync_edge_valid,
sp_control => sp_control,
sync_control => sync_control
sync_control => sync_control,
no_pos_resync => no_pos_resync
);
-- Temporary internal connections. Will be replaced during protocol
-- control re-work!
sample_nbt <= sample_nbt_i(2);
sample_dbt <= sample_dbt_i(2);
sample_nbt_del_1 <= sample_nbt_i(1);
sample_dbt_del_1 <= sample_dbt_i(1);
sample_nbt_del_2 <= sample_nbt_i(0);
sample_dbt_del_2 <= sample_dbt_i(0);
sync_nbt_del_1 <= sync_nbt_i(0);
sync_dbt_del_1 <= sync_dbt_i(0);
sync_nbt <= sync_nbt_i(1);
sync_dbt <= sync_dbt_i(1);
bus_sampling_comp : bus_sampling
generic map (
......@@ -854,10 +880,6 @@ begin
log_state_out <= config;
end generate event_logger_gen_false;
--Bit time clock output propagation
time_quanta_clk <= clk_tq_nbt when sp_control = NOMINAL_SAMPLE else
clk_tq_dbt;
OP_State <= oper_mode_type'val(to_integer(unsigned(
stat_bus(STAT_OP_STATE_HIGH downto STAT_OP_STATE_LOW))));
......
......@@ -860,12 +860,54 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_cfg_capture.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_counters.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_fsm.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/prescaler.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/resynchronisation.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/segment_end_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/synchronisation_checker.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/trigger_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>rx_buffer/rx_buffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1296,6 +1338,27 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_cfg_capture.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_counters.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/bit_time_fsm.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/prescaler.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1303,6 +1366,34 @@
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/resynchronisation.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/segment_end_detector.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/synchronisation_checker.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>prescaler/trigger_generator.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>rx_buffer/rx_buffer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......
......@@ -509,10 +509,8 @@ begin
if (i = 17) then
case bt_FSM is
when sync => bit_type_vect <= "0001";
when prop => bit_type_vect <= "0010";
when ph1 => bit_type_vect <= "0100";
when ph2 => bit_type_vect <= "1000";
when tseg1 => bit_type_vect <= "0001";
when tseg2 => bit_type_vect <= "1000";
when others => bit_type_vect <= "0000";
end case;
end if;
......
This diff is collapsed.
......@@ -123,11 +123,8 @@ package can_types is
);
type bit_time_type is (
sync,
prop,
ph1,
ph2,
h_sync,
tseg1,
tseg2,
reset
);
......
This diff is collapsed.
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Contains two counters:
-- 1. Time Quanta counter.
-- 2. Bit time counter.
--
-- Time Quanta counter counts duration of Time quanta segment and provides
--- Time Quanta edge signal.
-- Bit Time counter counts with granularity of Time Quanta and provides value
-- of Bit Time counter to the output.
--
--------------------------------------------------------------------------------
-- Revision History:
-- 15.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bit_time_counters is
generic (
-- Reset polarity
reset_polarity : std_logic := '0';
-- Bit Time counter width
bt_width : natural := 8;
-- Time Qunata counter width
tq_width : natural := 8
);
port(
-----------------------------------------------------------------------
-- Clock and reset
-----------------------------------------------------------------------
signal clk_sys : in std_logic;
signal res_n : in std_logic;
-----------------------------------------------------------------------
-- Control signals
-----------------------------------------------------------------------
-- Prescaler value
signal prescaler : in std_logic_vector(tq_width - 1 downto 0);
-- Time Quanta reset (synchronous)
signal tq_reset : in std_logic;
-- Bit Time reset (synchronous)
signal bt_reset : in std_logic;
-- Core is enabled
signal drv_ena : in std_logic;
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- Time Quanta edge
signal tq_edge : out std_logic;
-- Bit Time counter
signal bt_counter : out std_logic_vector(bt_width - 1 downto 0)
);
end entity;
architecture rtl of bit_time_counters is
-- Time Quanta Counter
signal tq_counter_d : std_logic_vector(tq_width - 1 downto 0);
signal tq_counter_q : std_logic_vector(tq_width - 1 downto 0);
signal tq_counter_ce : std_logic;
signal tq_edge_i : std_logic;
constant tq_zeroes : std_logic_vector(tq_width - 1 downto 0) :=
(OTHERS => '0');
constant tq_run_th : std_logic_vector(tq_width - 1 downto 0) :=
(0 => '1', OTHERS => '0');
-- Bit Time counter
signal bt_counter_d : std_logic_vector(bt_width - 1 downto 0);
signal bt_counter_q : std_logic_vector(bt_width - 1 downto 0);
constant bt_zeroes : std_logic_vector(bt_width - 1 downto 0) :=
(OTHERS => '0');
begin
---------------------------------------------------------------------------
-- If prescaler is defined as 0 or 1, there is no need to run the counter!
-- Run it only when Prescaler is higher than 1!
---------------------------------------------------------------------------
tq_counter_ce <= '1' when (prescaler > tq_run_th and drv_ena = '1') else
'0';
---------------------------------------------------------------------------
-- Time quanta counter next value:
-- 1. Erase when reaching value of prescaler.
-- 2. Erase when re-started.
-- 3. Add 1 ohterwise!
---------------------------------------------------------------------------
tq_counter_d <=
(OTHERS => '0') when (unsigned(tq_counter_q) = unsigned(prescaler) - 1)
else
(OTHERS => '0') when (tq_reset = '1')
else
std_logic_vector(unsigned(tq_counter_q) + 1);
tq_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
tq_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if (tq_counter_ce = '1') then
tq_counter_q <= tq_counter_d;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Time quanta edge
---------------------------------------------------------------------------
tq_edge_i <= '1' when (tq_counter_ce = '0' or
unsigned(tq_counter_q) = unsigned(prescaler) - 1)
else
'0';
---------------------------------------------------------------------------
-- Bit time counter
---------------------------------------------------------------------------
bt_counter_d <= bt_zeroes when (bt_reset = '1') else
std_logic_vector(unsigned(bt_counter_q) + 1);
bt_counter_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
bt_counter_q <= (OTHERS => '0');
elsif (rising_edge(clk_sys)) then
if ((tq_edge_i = '1' and drv_ena = '1') or bt_reset = '1') then
bt_counter_q <= bt_counter_d;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Internal signals to output propagation
---------------------------------------------------------------------------
bt_counter <= bt_counter_q;
tq_edge <= tq_edge_i;
end architecture rtl;
\ No newline at end of file
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Bit time FSM.
--
-- Bit Time FSM has three states:
-- 1. Reset
-- 2. TSEG1
-- 3. TSEG2
--
-- Output of Bit time FSM are SYNC and SAMPLE requests for SYNC and SAMPLE
-- trigger generator.
--------------------------------------------------------------------------------
-- Revision History:
-- 15.02.2019 Created file
--------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use ieee.math_real.ALL;
Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.endian_swap.all;
use work.reduce_lib.all;
use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
entity bit_time_fsm is
generic (
-- Reset polarity
reset_polarity : std_logic := '0'
);
port(
-----------------------------------------------------------------------
-- Clock and reset
-----------------------------------------------------------------------
signal clk_sys : in std_logic;
signal res_n : in std_logic;
-----------------------------------------------------------------------
-- Control interface
-----------------------------------------------------------------------
-- Signalling segment end (either due to re-sync, or reaching expected
-- length of segment)
signal segm_end : in std_logic;
signal h_sync_valid : in std_logic;
-- Core is enabled
signal drv_ena : in std_logic;
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- Bit time is in TSEG1
signal is_tseg1 : out std_logic;
-- Bit time is in TSEG2
signal is_tseg2 : out std_logic;
-- Sample point request (to sample point generator)
signal sample_req : out std_logic;
-- Sync signal request
signal sync_req : out std_logic;
-- Bit time FSM output
signal bt_FSM_out : out bit_time_type
);
end entity;
architecture rtl of bit_time_fsm is
-- Bit time FSM
signal current_state : bit_time_type;
signal next_state : bit_time_type;
-- Bit time FSM clock enable
signal bt_fsm_ce : std_logic;
begin
----------------------------------------------------------------------------
-- Next state process (combinational)
----------------------------------------------------------------------------
next_state_proc : process(current_state, h_sync_valid, segm_end, drv_ena)
begin
next_state <= current_state;
if (drv_ena = CTU_CAN_DISABLED) then
next_state <= reset;
elsif (h_sync_valid = '1') then
next_state <= tseg1;
else
case current_state is
when tseg1 =>
if (segm_end = '1') then
next_state <= tseg2;
end if;
when tseg2 =>
if (segm_end = '1') then
next_state <= tseg1;
end if;
when reset =>
next_state <= tseg1;
end case;
end if;
end process;
-- State register to output propagation
bt_FSM_out <= current_state;
----------------------------------------------------------------------------
-- Current state process (combinational)
----------------------------------------------------------------------------
curr_state_proc : process(current_state, segm_end)
begin
-- Default values
is_tseg1 <= '0';
is_tseg2 <= '0';
sample_req <= '0';
sync_req <= '0';
case current_state is
when reset =>
if (drv_ena = CTU_CAN_ENABLED) then
sync_req <= '1';
end if;
when tseg1 =>
is_tseg1 <= '1';
if (segm_end = '1') then
sample_req <= '1';
end if;
when tseg2 =>
is_tseg2 <= '1';
if (segm_end = '1') then
sync_req <= '1';
end if;
end case;
end process;
----------------------------------------------------------------------------
-- State register assignment
----------------------------------------------------------------------------
state_reg_proc : process(clk_sys, res_n)
begin
if (res_n = reset_polarity) then
current_state <= reset;
elsif (rising_edge(clk_sys)) then
if (bt_fsm_ce = '1') then
current_state <= next_state;