Commit 1ab1fd1d authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Updated Vivado project

parent aa2fd244
......@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Tue Apr 24 09:33:28 2018">
<application name="pa" timeStamp="Mon Jul 9 13:54:54 2018">
<section name="Project Information" visible="false">
<property name="ProjectID" value="151929edaff848b780e40a893552cd2f" type="ProjectID"/>
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
......@@ -17,46 +17,76 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="AddSources" value="2" type="JavaHandler"/>
<property name="EditDelete" value="3" type="JavaHandler"/>
<property name="ReportTimingSummary" value="1" type="JavaHandler"/>
<property name="ResetLayout" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="2" type="JavaHandler"/>
<property name="RunSchematic" value="3" type="JavaHandler"/>
<property name="RunSynthesis" value="1" type="JavaHandler"/>
<property name="RunSynthesis" value="3" type="JavaHandler"/>
<property name="ShowPowerEstimation" value="1" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
<property name="ShowView" value="4" type="JavaHandler"/>
<property name="TclStore" value="1" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="6" type="JavaHandler"/>
<property name="ZoomIn" value="13" type="JavaHandler"/>
<property name="ZoomOut" value="7" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="29" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="37" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_ADD_FILES" value="1" type="GuiHandlerData"/>
<property name="ExpReportTreePanel_EXP_REPORT_TREE_TABLE" value="1" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="14" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="39" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="20" type="GuiHandlerData"/>
<property name="ExpRunMenu_LAUNCH_RUNS" value="2" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="25" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="87" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="27" type="GuiHandlerData"/>
<property name="GraphicalView_NEXT" value="1" type="GuiHandlerData"/>
<property name="HExceptionDialog_CONTINUE" value="1" type="GuiHandlerData"/>
<property name="InstanceMenu_FLOORPLANNING" value="1" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="3" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="3" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="6" type="GuiHandlerData"/>
<property name="LogMonitor_MONITOR" value="38" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOORPLANNING" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="4" type="GuiHandlerData"/>
<property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_IO_PLANNING" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TIMING" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="12" type="GuiHandlerData"/>
<property name="MainMenuMgr_VIEW" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="16" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="5" type="GuiHandlerData"/>
<property name="MainWinMenuMgr_LAYOUT" value="12" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="29" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="6" type="GuiHandlerData"/>
<property name="NetlistSchematicView_SHOW_CELLS_IN_THIS_SCHEMATIC" value="2" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_CLOCK_REGIONS_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_GOTO_NETLIST_DESIGN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_BITGEN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_IMPLEMENTATION" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SCHEMATIC" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_TCL_CONSOLE_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_TCL_STORE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_IN" value="14" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="8" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="2" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="4" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="3" type="GuiHandlerData"/>
<property name="PrimitivesMenu_HIGHLIGHT_LEAF_CELLS" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="ProjectTab_CLOSE_DESIGN" value="2" type="GuiHandlerData"/>
<property name="RDICommands_CUSTOM_COMMANDS" value="3" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="3" type="GuiHandlerData"/>
<property name="RDICommands_PASTE" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_GROUP" value="1" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="3" type="GuiHandlerData"/>
<property name="SchematicView_PREVIOUS" value="10" type="GuiHandlerData"/>
......@@ -64,14 +94,21 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SelectMenu_MARK" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_OPTIONS_TREE" value="1" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="5" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="7" type="GuiHandlerData"/>
<property name="SrcMenu_OPEN_SELECTED_SOURCE_FILES" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_COPY" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="23" type="GuiHandlerData"/>
<property name="TclStoreDialog_CLOSE" value="1" type="GuiHandlerData"/>
<property name="TclStoreDialog_TCL_STORE_NAVIGATOR" value="1" type="GuiHandlerData"/>
<property name="XPowerSettingsDialog_CANCEL" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="5" type="GuiMode"/>
<property name="GuiMode" value="9" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="3" type="TclMode"/>
<property name="TclMode" value="4" type="TclMode"/>
</item>
</section>
</application>
......
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
reset_param project.defaultXPMLibraries
open_checkpoint /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/CAN_top_level.dcp
set_property webtalk.parent_dir /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/wt [current_project]
set_property parent.project_path /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.xpr [current_project]
set_property ip_output_repo /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force CAN_top_level_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file CAN_top_level_drc_opted.rpt -pb CAN_top_level_drc_opted.pb -rpx CAN_top_level_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
implement_debug_core
place_design
write_checkpoint -force CAN_top_level_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file CAN_top_level_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file CAN_top_level_utilization_placed.rpt -pb CAN_top_level_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CAN_top_level_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force CAN_top_level_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file CAN_top_level_drc_routed.rpt -pb CAN_top_level_drc_routed.pb -rpx CAN_top_level_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file CAN_top_level_methodology_drc_routed.rpt -pb CAN_top_level_methodology_drc_routed.pb -rpx CAN_top_level_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file CAN_top_level_power_routed.rpt -pb CAN_top_level_power_summary_routed.pb -rpx CAN_top_level_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file CAN_top_level_route_status.rpt -pb CAN_top_level_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CAN_top_level_timing_summary_routed.rpt -warn_on_violation -rpx CAN_top_level_timing_summary_routed.rpx"
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CAN_top_level_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CAN_top_level_clock_utilization_routed.rpt"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force CAN_top_level_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
#
vivado -log CAN_top_level.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CAN_top_level.tcl -notrace
#-----------------------------------------------------------
# Vivado v2017.3 (64-bit)
# SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
# IP Build 2016188 on Wed Oct 4 21:52:56 MDT 2017
# Start of session at: Thu Apr 19 18:30:37 2018
# Process ID: 28645
# Current directory: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1
# Command line: vivado -log CAN_top_level.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CAN_top_level.tcl -notrace
# Log file: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/CAN_top_level.vdi
# Journal file: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/impl_1/vivado.jou
#-----------------------------------------------------------
source CAN_top_level.tcl -notrace
......@@ -39,6 +39,7 @@ read_vhdl -library xil_defaultlib {
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Buffers_Message_Handling/messageFilter.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/Interrupts/intManager.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/operationControl.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/endian_swap.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/protocolControl.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/faultConf.vhd
/DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/src/CAN_Core/CRC.vhd
......@@ -61,6 +62,9 @@ read_vhdl -library xil_defaultlib {
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc
set_property used_in_implementation false [get_files /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Constraints/CTU_CAN_FD_Xilinx.sdc]
synth_design -top CAN_top_level -part xc7z007sclg225-2
......
This source diff could not be displayed because it is too large. You can view the blob instead.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
| Date : Thu Apr 19 18:23:10 2018
| Date : Mon Jul 9 13:57:24 2018
| Host : ondrej-Aspire-V3-771 running 64-bit Ubuntu 16.04.4 LTS
| Command : report_utilization -file CAN_top_level_utilization_synth.rpt -pb CAN_top_level_utilization_synth.pb
| Design : CAN_top_level
......@@ -30,16 +30,16 @@ Table of Contents
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs* | 3126 | 0 | 14400 | 21.71 |
| LUT as Logic | 2930 | 0 | 14400 | 20.35 |
| LUT as Memory | 196 | 0 | 6000 | 3.27 |
| LUT as Distributed RAM | 196 | 0 | | |
| Slice LUTs* | 3131 | 0 | 14400 | 21.74 |
| LUT as Logic | 2999 | 0 | 14400 | 20.83 |
| LUT as Memory | 132 | 0 | 6000 | 2.20 |
| LUT as Distributed RAM | 132 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 1836 | 0 | 28800 | 6.38 |
| Register as Flip Flop | 1836 | 0 | 28800 | 6.38 |
| Slice Registers | 1894 | 0 | 28800 | 6.58 |
| Register as Flip Flop | 1894 | 0 | 28800 | 6.58 |
| Register as Latch | 0 | 0 | 28800 | 0.00 |
| F7 Muxes | 44 | 0 | 8800 | 0.50 |
| F8 Muxes | 18 | 0 | 4400 | 0.41 |
| F7 Muxes | 88 | 0 | 8800 | 1.00 |
| F8 Muxes | 21 | 0 | 4400 | 0.48 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
......@@ -56,10 +56,10 @@ Table of Contents
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 199 | Yes | - | Set |
| 1618 | Yes | - | Reset |
| 200 | Yes | - | Set |
| 1684 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 19 | Yes | Reset | - |
| 10 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
......@@ -149,23 +149,23 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 1618 | Flop & Latch |
| LUT6 | 1418 | LUT |
| LUT2 | 774 | LUT |
| LUT4 | 610 | LUT |
| LUT5 | 424 | LUT |
| LUT3 | 424 | LUT |
| FDPE | 199 | Flop & Latch |
| RAMD32 | 130 | Distributed Memory |
| FDCE | 1684 | Flop & Latch |
| LUT6 | 1499 | LUT |
| LUT2 | 758 | LUT |
| LUT4 | 616 | LUT |
| LUT5 | 472 | LUT |
| LUT3 | 378 | LUT |
| FDPE | 200 | Flop & Latch |
| CARRY4 | 127 | CarryLogic |
| IBUF | 126 | IO |
| CARRY4 | 126 | CarryLogic |
| RAMD64E | 88 | Distributed Memory |
| MUXF7 | 44 | MuxFx |
| MUXF7 | 88 | MuxFx |
| RAMD32 | 66 | Distributed Memory |
| OBUF | 35 | IO |
| LUT1 | 32 | LUT |
| LUT1 | 33 | LUT |
| RAMS32 | 22 | Distributed Memory |
| FDRE | 19 | Flop & Latch |
| MUXF8 | 18 | MuxFx |
| MUXF8 | 21 | MuxFx |
| FDRE | 10 | Flop & Latch |
| RAMB18E1 | 4 | Block Memory |
| BUFG | 1 | Clock |
+----------+------+---------------------+
......
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z007sclg225-2" LaunchTime="1524154889">
<GenRun Id="synth_1" LaunchPart="xc7z007sclg225-2" LaunchTime="1531137294">
<File Type="VDS-TIMING-PB" Name="CAN_top_level_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="CAN_top_level_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="CAN_top_level.dcp"/>
<File Type="RDS-UTIL-PB" Name="CAN_top_level_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="CAN_top_level_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="CAN_top_level_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="CAN_top_level.vds"/>
<File Type="REPORTS-TCL" Name="CAN_top_level_reports.tcl"/>
<File Type="PA-TCL" Name="CAN_top_level.tcl"/>
<File Type="RDS-RDS" Name="CAN_top_level.vds"/>
<File Type="RDS-PROPCONSTRS" Name="CAN_top_level_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="CAN_top_level_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="CAN_top_level_utilization_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../../src/Libraries/CAN_FD_frame_format.vhd">
......@@ -77,6 +77,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/endian_swap.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/CAN_Core/protocolControl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -155,27 +161,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/bitStuffing.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/timeStampGen.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/txBuffer.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CAN_top_level"/>
......@@ -184,14 +169,18 @@
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../../Constraints/CTU_CAN_FD_Xilinx.sdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
......@@ -2,8 +2,8 @@
# Vivado v2017.3 (64-bit)
# SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
# IP Build 2016188 on Wed Oct 4 21:52:56 MDT 2017
# Start of session at: Thu Apr 19 18:21:31 2018
# Process ID: 27518
# Start of session at: Mon Jul 9 13:54:56 2018
# Process ID: 14570
# Current directory: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1
# Command line: vivado -log CAN_top_level.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CAN_top_level.tcl
# Log file: /DOKUMENTY/Skola/CVUT-FEL/CAN_FD_IP_Core/synthesis/Vivado/xilinx_benchmark/xilinx_benchmark.runs/synth_1/CAN_top_level.vds
......
......@@ -122,6 +122,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/endian_swap.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/CAN_Core/protocolControl.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
......@@ -200,27 +206,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/bitStuffing.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/timeStampGen.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../src/Deprecated/txBuffer.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CAN_top_level"/>
......@@ -229,11 +214,18 @@
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../../Constraints/CTU_CAN_FD_Xilinx.sdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="CAN_top_level"/>
......@@ -269,9 +261,7 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z007sclg225-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -286,11 +276,9 @@
</ReportStrategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z007sclg225-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z007sclg225-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
......@@ -301,16 +289,15 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017">
<ReportConfig Name="impl_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig Name="impl_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="CAN_top_level_drc_opted.rpt" Version="1" Minor="0">
<ReportConfig Name="impl_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value="CAN_top_level_drc_opted.pb"/>
<ReportConfigOutputOption Name="rpx" Type="string" Value="CAN_top_level_drc_opted.rpx"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig Name="impl_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
......
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