Commit 0ec9c8ef authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '259-can-address-dependency' into 'master'

Resolve "CAN address dependency"

Closes #259

See merge request !240
parents 1ca73e22 5b38eb00
Pipeline #6790 passed with stage
in 43 seconds
......@@ -506,12 +506,6 @@ CTU CAN FD IP Core
\begin_inset Text
\begin_layout Plain Layout
\begin_inset CommandInset include
LatexCommand input
filename "version.tex"
\end_inset
\end_layout
......@@ -533,7 +527,7 @@ Ille Ondrej, Martin Jeřábek
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="8" columns="4">
<lyxtabular version="3" rows="9" columns="4">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="1.5cm">
<column alignment="center" valignment="top" width="2cm">
......@@ -812,13 +806,51 @@ Added CRC Wrapper.
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
2.1.3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Ondrej Ille
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
01-2019
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Added TIMESTAMP_LOW, TIMESTAMP_HIGH registers.
\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
2.1.4
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
......@@ -834,7 +866,7 @@ Ondrej Ille
\begin_inset Text
\begin_layout Plain Layout
01-2019
02-2019
\end_layout
\end_inset
......@@ -843,7 +875,7 @@ Ondrej Ille
\begin_inset Text
\begin_layout Plain Layout
Added TIMESTAMP_LOW, TIMESTAMP_HIGH registers.
Removed 0x3 in bits 23:20 of address.
\end_layout
\end_inset
......@@ -1943,10 +1975,6 @@ ID
With this architecture, it is possible to create up to 16 instances on
a single parallel memory bus.
More cores can be instantiated when using Interconnect components.
Address bits 23:20 must have constant value 0x3.
This requirement is given by a custom system for which this core was originally
developed.
Description of this system is beyond the scope of this document.
\end_layout
\begin_layout Standard
......@@ -1959,26 +1987,16 @@ status open
\noindent
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="2" columns="3">
<lyxtabular version="3" rows="2" columns="2">
<features tabularvalignment="middle">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<column alignment="center" valignment="top">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 23:20
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 19:16
Avalon Address 15:12
\end_layout
\end_inset
......@@ -1987,7 +2005,7 @@ Avalon Address 19:16
\begin_inset Text
\begin_layout Plain Layout
Avalon Address 15:0
Avalon Address 11:0
\end_layout
\end_inset
......@@ -1997,15 +2015,6 @@ Avalon Address 15:0
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
0x3
\end_layout
\end_inset
</cell>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\family roman
......@@ -2639,7 +2648,7 @@ in
\begin_inset Text
\begin_layout Plain Layout
24
16
\end_layout
\end_inset
......
......@@ -81,7 +81,7 @@ entity apb_ifc is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......@@ -119,9 +119,6 @@ begin
reg_data_in_o <= s_apb_pwdata;
s_apb_prdata <= reg_data_out_i;
reg_addr_o(COMP_TYPE_ADRESS_HIGHER downto COMP_TYPE_ADRESS_LOWER) <=
CAN_COMPONENT_TYPE;
reg_addr_o(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) <=
std_logic_vector(to_unsigned(ID, 4));
......
......@@ -104,7 +104,7 @@ architecture rtl of CTU_CAN_FD_v1_0 is
signal reg_data_in : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal reg_addr : std_logic_vector(23 downto 0);
signal reg_addr : std_logic_vector(15 downto 0);
signal reg_be : std_logic_vector(3 downto 0);
signal reg_rden : std_logic;
signal reg_wren : std_logic;
......
......@@ -129,7 +129,7 @@ entity can_top_level is
---------------------
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic; --Chip select
signal srd : in std_logic; --Serial read
signal swr : in std_logic; --Serial write
......@@ -512,7 +512,6 @@ begin
memory_registers_comp : memory_registers
generic map(
compType => CAN_COMPONENT_TYPE,
use_logger => use_logger,
sup_filtA => sup_filtA,
sup_filtB => sup_filtB,
......
......@@ -86,7 +86,7 @@ package can_components is
signal res_n : in std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -116,7 +116,6 @@ package can_components is
----------------------------------------------------------------------------
component memory_registers is
generic(
constant compType : std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
constant use_logger : boolean := true;
constant sup_filtA : boolean := true;
constant sup_filtB : boolean := true;
......@@ -135,7 +134,7 @@ package can_components is
signal res_out : out std_logic;
signal data_in : in std_logic_vector(31 downto 0);
signal data_out : out std_logic_vector(31 downto 0);
signal adress : in std_logic_vector(23 downto 0);
signal adress : in std_logic_vector(15 downto 0);
signal scs : in std_logic;
signal srd : in std_logic;
signal swr : in std_logic;
......@@ -1164,7 +1163,7 @@ package can_components is
reg_data_in_o : out std_logic_vector(31 downto 0);
reg_data_out_i : in std_logic_vector(31 downto 0);
reg_addr_o : out std_logic_vector(23 downto 0);
reg_addr_o : out std_logic_vector(15 downto 0);
reg_be_o : out std_logic_vector(3 downto 0);
reg_rden_o : out std_logic;
reg_wren_o : out std_logic;
......
......@@ -154,30 +154,13 @@ package can_constants is
----------------------------------------------------------------------------
-- Memory Access
----------------------------------------------------------------------------
-- General Purpose register
constant GPR_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"1";
-- OutPut Multiplexor component type
constant OUTMUX_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"2";
-- FlexRay Node
constant FLEXRAY_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"3";
-- CAN Node
constant CAN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"4";
-- LIN Node
constant LIN_COMPONENT_TYPE : std_logic_vector(3 downto 0) := x"5";
constant ACT_CSC : std_logic := '1';
constant ACT_SRD : std_logic := '1';
constant ACT_SWR : std_logic := '1';
-- Address ranges for component type and identifier
constant COMP_TYPE_ADRESS_HIGHER : natural := 23;
constant COMP_TYPE_ADRESS_LOWER : natural := 20;
constant ID_ADRESS_HIGHER : natural := 19;
constant ID_ADRESS_LOWER : natural := 16;
-- Address ranges for identifier
constant ID_ADRESS_HIGHER : natural := 15;
constant ID_ADRESS_LOWER : natural := 12;
constant CAN_DEVICE_ID : std_logic_vector(31 downto 0) := x"0000CAFD";
......
......@@ -148,8 +148,6 @@ use work.can_registers_pkg.all;
entity memory_registers is
generic(
constant compType :std_logic_vector(3 downto 0) := CAN_COMPONENT_TYPE;
-- Whenever event logger is present
constant use_logger :boolean := true;
......@@ -190,7 +188,7 @@ entity memory_registers is
------------------------------------------------------------------------
signal data_in :in std_logic_vector(31 downto 0);
signal data_out :out std_logic_vector(31 downto 0);
signal adress :in std_logic_vector(23 downto 0);
signal adress :in std_logic_vector(15 downto 0);
signal scs :in std_logic;
signal srd :in std_logic;
signal swr :in std_logic;
......@@ -392,8 +390,6 @@ begin
end generate txtb_cs_gen;
can_core_cs <= '1' when (scs = ACT_CSC) and
(adress(COMP_TYPE_ADRESS_HIGHER downto
COMP_TYPE_ADRESS_LOWER) = compType) and
(adress(ID_ADRESS_HIGHER downto ID_ADRESS_LOWER) =
std_logic_vector(to_unsigned(ID, 4)))
else
......@@ -446,7 +442,7 @@ begin
control_registers_reg_map_comp : control_registers_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
REGISTERED_READ => true,
CLEAR_READ_DATA => true,
RESET_POLARITY => ACT_RESET,
......@@ -480,7 +476,7 @@ begin
event_logger_reg_map_comp : event_logger_reg_map
generic map(
DATA_WIDTH => 32,
ADDRESS_WIDTH => 24,
ADDRESS_WIDTH => 16,
CLEAR_READ_DATA => true,
REGISTERED_READ => true,
RESET_POLARITY => ACT_RESET
......
......@@ -120,7 +120,7 @@ architecture feature_env_test of CAN_feature_test is
data_in : std_logic_vector(31 downto 0);
data_out : std_logic_vector(31 downto 0);
adress : std_logic_vector(23 downto 0);
adress : std_logic_vector(15 downto 0);
scs : std_logic; --Chip select
srd : std_logic; --Serial read
swr : std_logic; --Serial write
......@@ -194,7 +194,7 @@ begin
-------------------------------------------------
x1: mem_bus(i).clk_sys <= p(i).clk_sys;
x2: p(i).data_in <= mem_bus(i).data_in;
x3: p(i).adress <= mem_bus(i).address;
x3: p(i).adress <= mem_bus(i).address(15 downto 0);
x4: p(i).scs <= mem_bus(i).scs;
x5: p(i).swr <= mem_bus(i).swr;
x6: p(i).srd <= mem_bus(i).srd;
......
This diff is collapsed.
......@@ -69,7 +69,7 @@ architecture CAN_reference_test of CAN_test is
signal timestamp : std_logic_vector(63 downto 0) := (OTHERS => '0');
signal data_in : std_logic_vector(31 downto 0) := (OTHERS => '0');
signal data_out : std_logic_vector(31 downto 0);
signal adress : std_logic_vector(23 downto 0) := (OTHERS => '0');
signal adress : std_logic_vector(15 downto 0) := (OTHERS => '0');
signal scs : std_logic := '0';
signal srd : std_logic := '0';
signal swr : std_logic := '0';
......@@ -304,7 +304,7 @@ begin
scs <= mem_bus.scs;
srd <= mem_bus.srd;
swr <= mem_bus.swr;
adress <= mem_bus.address;
adress <= mem_bus.address(15 downto 0);
data_in <= mem_bus.data_in;
mem_bus.data_out <= data_out;
......
......@@ -158,7 +158,7 @@ architecture behavioral of sanity_test is
array (1 to NODE_COUNT) of std_logic_vector(3 downto 0);
type mem_addr_arr_type is
array (1 to NODE_COUNT) of std_logic_vector(23 downto 0);
array (1 to NODE_COUNT) of std_logic_vector(15 downto 0);
signal mem_aux_data_in : mem_vect_arr_type :=
(OTHERS => (OTHERS => '0'));
......@@ -485,7 +485,7 @@ begin
mb_arr(i).clk_sys <= mem_aux_clk(i);
mem_aux_data_in(i) <= mb_arr(i).data_in;
mem_aux_address(i) <= mb_arr(i).address;
mem_aux_address(i) <= mb_arr(i).address(15 downto 0);
mem_aux_scs(i) <= mb_arr(i).scs;
mem_aux_swr(i) <= mb_arr(i).swr;
mem_aux_srd(i) <= mb_arr(i).srd;
......
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