1. There should be enough time after HW/POR reset before devices are
   accessed by OS/driver (it is 20 ns on 100 MHz!!)
2. Device does not answer for two clock cycles due to reset synchronizer!
   CAN FD reset is defined as async. reset. If there is countdown reset
   register reset by asynchronous reset, this leaves "countdown reset
   register" susceptible to reset recovery violations. So whole "post-reset"
   not ready thing will not work properly if there will be true async.
   reset (both asserted and deasserted as async). We would see random
   ready/not-ready indication based on how the metastability resolved on
   "countdown reset register".
   In the end, if SW did reset and tried to access immediately after that,
   sometimes transaction would be prolonged (and returned correct data
   afterwards), and sometimes it would finish and return crap. IMHO this
   is worse than writing to datasheet something like: device shall not
   be accessed two clock cycles after HW reset. BTW, I saw post reset
   delays in drivers for PCIe (like 1-2ms), though this was to give HW
   time to complete BIST...