user.org user CTU_CAN_FD 1.0 aclk CLK aclk ASSOCIATED_RESET arstn time_quanta_clk CLK time_quanta_clk irq INTERRUPT irq SENSITIVITY LEVEL_HIGH s_apb S_APB S_APB PADDR s_apb_paddr PPROT s_apb_pprot PSEL s_apb_psel PENABLE s_apb_penable PWRITE s_apb_pwrite PWDATA s_apb_pwdata PSTRB s_apb_pstrb PREADY s_apb_pready PRDATA s_apb_prdata PSLVERR s_apb_pslverr arstn RST arstn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL CTU_CAN_FD_v1_0 xilinx_anylanguagesynthesis_view_fileset viewChecksum bd93fd12 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL CTU_CAN_FD_v1_0 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum bd93fd12 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum aabbb6d4 aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation arstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation CAN_tx out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation CAN_rx in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation time_quanta_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation timestamp in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_paddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_penable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_prdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_psel in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pslverr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pwdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_apb_pwrite in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation use_logger Use Logger true rx_buffer_size Rx Buffer Size 128 use_sync Use Sync true sup_filtA Sup Filta true sup_filtB Sup Filtb true sup_filtC Sup Filtc true sup_range Sup Range true logger_size Logger Size 8 choice_list_99a1d2b9 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset apb/apb_ifc.vhd vhdlSource xil_defaultlib bus_sampling/bus_sampling.vhd vhdlSource xil_defaultlib bus_sampling/data_edge_detector.vhd vhdlSource xil_defaultlib bus_sampling/trv_delay_meas.vhd vhdlSource xil_defaultlib bus_sampling/tx_data_cache.vhd vhdlSource xil_defaultlib can_core/bit_destuffing/bit_destuffing.vhd vhdlSource xil_defaultlib can_core/bit_stuffing/bit_stuffing.vhd vhdlSource xil_defaultlib can_core/bus_traffic_counters/bus_traffic_counters.vhd vhdlSource xil_defaultlib can_core/can_core.vhd vhdlSource xil_defaultlib can_core/crc/can_crc.vhd vhdlSource xil_defaultlib can_core/crc/crc_calc.vhd vhdlSource xil_defaultlib can_core/crc/crc_wrapper.vhd vhdlSource xil_defaultlib can_core/fault_confinement/fault_confinement.vhd vhdlSource xil_defaultlib can_core/operation_control/operation_control.vhd vhdlSource xil_defaultlib can_core/protocol_control/protocol_control.vhd vhdlSource xil_defaultlib can_top_apb.vhd vhdlSource xil_defaultlib can_top_level.vhd vhdlSource xil_defaultlib common/dff_arst.vhd vhdlSource xil_defaultlib common/endian_swap.vhd vhdlSource xil_defaultlib common/endian_swapper.vhd vhdlSource xil_defaultlib common/inf_ram_wrapper.vhd vhdlSource xil_defaultlib common/majority_decoder_3.vhd vhdlSource xil_defaultlib common/rst_sync.vhd vhdlSource xil_defaultlib common/shift_reg.vhd vhdlSource xil_defaultlib common/shift_reg_preload.vhd vhdlSource xil_defaultlib common/sig_sync.vhd vhdlSource xil_defaultlib event_logger/event_logger.vhd vhdlSource xil_defaultlib frame_filters/bit_filter.vhd vhdlSource xil_defaultlib frame_filters/frame_filters.vhd vhdlSource xil_defaultlib frame_filters/range_filter.vhd vhdlSource xil_defaultlib interrupts/int_manager.vhd vhdlSource xil_defaultlib interrupts/int_module.vhd vhdlSource xil_defaultlib lib/can_components.vhd vhdlSource xil_defaultlib lib/can_constants.vhd vhdlSource xil_defaultlib lib/can_fd_frame_format.vhd vhdlSource xil_defaultlib lib/can_fd_register_map.vhd vhdlSource xil_defaultlib lib/can_types.vhd vhdlSource xil_defaultlib lib/cmn_lib.vhd vhdlSource xil_defaultlib lib/drv_stat_pkg.vhd vhdlSource xil_defaultlib lib/id_transfer.vhd vhdlSource xil_defaultlib lib/reduce_lib.vhd vhdlSource xil_defaultlib memory_registers/generated/access_signaler.vhd vhdlSource xil_defaultlib memory_registers/generated/address_decoder.vhd vhdlSource xil_defaultlib memory_registers/generated/can_registers_pkg.vhd vhdlSource xil_defaultlib memory_registers/generated/cmn_reg_map_pkg.vhd vhdlSource xil_defaultlib memory_registers/generated/control_registers_reg_map.vhd vhdlSource xil_defaultlib memory_registers/generated/data_mux.vhd vhdlSource xil_defaultlib memory_registers/generated/event_logger_reg_map.vhd vhdlSource xil_defaultlib memory_registers/generated/memory_bus.vhd vhdlSource xil_defaultlib memory_registers/generated/memory_reg.vhd vhdlSource xil_defaultlib memory_registers/memory_registers.vhd vhdlSource xil_defaultlib prescaler/prescaler.vhd vhdlSource xil_defaultlib rx_buffer/rx_buffer.vhd vhdlSource xil_defaultlib rx_buffer/rx_buffer_fsm.vhd vhdlSource xil_defaultlib rx_buffer/rx_buffer_pointers.vhd vhdlSource xil_defaultlib tx_arbitrator/priority_decoder.vhd vhdlSource xil_defaultlib tx_arbitrator/tx_arbitrator.vhd vhdlSource xil_defaultlib tx_arbitrator/tx_arbitrator_fsm.vhd vhdlSource xil_defaultlib txt_buffer/txt_buffer.vhd vhdlSource xil_defaultlib txt_buffer/txt_buffer_fsm.vhd vhdlSource xil_defaultlib xilinx_anylanguagebehavioralsimulation_view_fileset apb/apb_ifc.vhd vhdlSource USED_IN_ipstatic xil_defaultlib bus_sampling/bus_sampling.vhd vhdlSource USED_IN_ipstatic xil_defaultlib bus_sampling/data_edge_detector.vhd vhdlSource USED_IN_ipstatic xil_defaultlib bus_sampling/trv_delay_meas.vhd vhdlSource USED_IN_ipstatic xil_defaultlib bus_sampling/tx_data_cache.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/bit_destuffing/bit_destuffing.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/bit_stuffing/bit_stuffing.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/bus_traffic_counters/bus_traffic_counters.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/can_core.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/crc/can_crc.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/crc/crc_calc.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/crc/crc_wrapper.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/fault_confinement/fault_confinement.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/operation_control/operation_control.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_core/protocol_control/protocol_control.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_top_apb.vhd vhdlSource USED_IN_ipstatic xil_defaultlib can_top_level.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/dff_arst.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/endian_swap.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/endian_swapper.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/inf_ram_wrapper.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/majority_decoder_3.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/rst_sync.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/shift_reg.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/shift_reg_preload.vhd vhdlSource USED_IN_ipstatic xil_defaultlib common/sig_sync.vhd vhdlSource USED_IN_ipstatic xil_defaultlib event_logger/event_logger.vhd vhdlSource USED_IN_ipstatic xil_defaultlib frame_filters/bit_filter.vhd vhdlSource USED_IN_ipstatic xil_defaultlib frame_filters/frame_filters.vhd vhdlSource USED_IN_ipstatic xil_defaultlib frame_filters/range_filter.vhd vhdlSource USED_IN_ipstatic xil_defaultlib interrupts/int_manager.vhd vhdlSource USED_IN_ipstatic xil_defaultlib interrupts/int_module.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/can_components.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/can_constants.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/can_fd_frame_format.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/can_fd_register_map.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/can_types.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/cmn_lib.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/drv_stat_pkg.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/id_transfer.vhd vhdlSource USED_IN_ipstatic xil_defaultlib lib/reduce_lib.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/access_signaler.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/address_decoder.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/can_registers_pkg.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/cmn_reg_map_pkg.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/control_registers_reg_map.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/data_mux.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/event_logger_reg_map.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/memory_bus.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/generated/memory_reg.vhd vhdlSource USED_IN_ipstatic xil_defaultlib memory_registers/memory_registers.vhd vhdlSource USED_IN_ipstatic xil_defaultlib prescaler/prescaler.vhd vhdlSource USED_IN_ipstatic xil_defaultlib rx_buffer/rx_buffer.vhd vhdlSource USED_IN_ipstatic xil_defaultlib rx_buffer/rx_buffer_fsm.vhd vhdlSource USED_IN_ipstatic xil_defaultlib rx_buffer/rx_buffer_pointers.vhd vhdlSource USED_IN_ipstatic xil_defaultlib tx_arbitrator/priority_decoder.vhd vhdlSource USED_IN_ipstatic xil_defaultlib tx_arbitrator/tx_arbitrator.vhd vhdlSource USED_IN_ipstatic xil_defaultlib tx_arbitrator/tx_arbitrator_fsm.vhd vhdlSource USED_IN_ipstatic xil_defaultlib txt_buffer/txt_buffer.vhd vhdlSource USED_IN_ipstatic xil_defaultlib txt_buffer/txt_buffer_fsm.vhd vhdlSource USED_IN_ipstatic xil_defaultlib xilinx_xpgui_view_fileset xgui/CTU_CAN_FD_v1_0.tcl tclSource CHECKSUM_aabbb6d4 XGUI_VERSION_2 CTU_CAN_FD_v1_0 use_logger Use Logger true rx_buffer_size Rx Buffer Size 128 use_sync Use Sync true sup_filtA Sup Filta true sup_filtB Sup Filtb true sup_filtC Sup Filtc true sup_range Sup Range true logger_size Logger Size 8 Component_Name CTU_CAN_FD_v1_0 zynq qzynq azynq /UserIP CTU_CAN_FD_v1_0 package_project 4 2019-01-07T11:37:47Z /home/pi/fpga/zynq/canbech-sw/modules/CTU_CAN_FD/src 2017.4