CTU ip CAN_FD_IP_Core 2.1 CAN_Registers CAN FD Core memory map CTU CAN FD IP Core is designed as 32 bit peripheria with byte enable support for 8, 16 or 32 bit access. Unaligned access is not supported. Byte or half word access is executed via byte enable signal. The memory is organized as Big endian. Write to read only memory location will have no effect. Read from write only memory location will return zeroes. The memory map consists of following memory regions: Control_registers Control registers Control registers memory region. 'h0 256 32 register true DEVICE_ID DEVICE ID Register contains the identifer of CTU CAN FD IP Core. It can be used to determine if CTU CAN FD IP Core is mapped correctly on its base address. 0 'h0 16 true read-only DEVICE_ID DEVICE_ID Device ID 0 'hCAFD 16 read-only CTU_CAN_FD_ID CTU_CAN_FD_DEVICE_ID Identifier of CTU CAN FD IP Core. 'hCAFD MODE MODE MODE register controls operating modes. 0 'h4 8 true read-write RST RST Writing logic 1 resets the core. It has the same effect as logic 0 on "res_n" input of the controller. After writing logic 1, logic 0 does not need to be written, this bit is automatically cleared. 0 0 1 clear FDE FDE Enable flexible data rate support. When disabled, receiving recessive EDL bit (Flexible data-rate frame) causes Form error. This bit does not affect capability to transmitt FD Frames. 4 1 1 FDE_ENABLE FDE_ENABLE Flexible data-rate support enabled. 1 FDE_DISABLE FDE_DISABLE Flexible data-rate support disabled. 0 TSM TSM Tripple sampling mode. Bus value is sampled three times when this mode is enabled. Even if this bit is set, triple sampling is used only during Nominal data rate. CAN standard reccomends to use tripple sampling at low Bit rates. 6 0 1 TSM_ENABLE TSM_ENABLE Tripple sampling mode enabled 1 TSM_DISABLE TSM_DISABLE Tripple sampling mode disabled 0 RTRP RTR_PREFFERED RTR Frame preferred behavior. When RTR frame is sent non-zero dlc code can be inserted. This bit specifies the behavior of controller when sending RTR Frames. 5 1 1 RTR_STANDARD RTR_STANDARD When RTR Frame is sent, also the DLC inserted to TX Buffer is sent. 1 RTR_EXTRA RTR_EXTRA When RTR Frame is sent, all zeroes are sent at DLC. 0 ACF ACF Acknowledge forbidden mode. When this mode is enabled, acknowledge is not sent even if received CRC matches the calculated one. 7 0 1 ACF_ENABLED ACF_ENABLED Acknowledge forbidden mode enabled. 1 ACF_DISABLED ACF_DISABLED Acknowledge forbidden mode disabled. 0 LOM LOM Listen only mode. In this mode controller only receives data and sends only recessive bits on the bus. When a dominant bus is sent it is rerouted internally so that bus value remains the same. Note that when this mode is enabled controller will not transmit any inserted frame! 1 0 1 LOM_ENABLED LOM_ENABLED Listen only mode enabled. 1 LOM_DISABLED LOM_DISABLED Listen only mode disabled. 0 STM STM Self test mode. In this mode transmitted frame is considered valid even if acknowledge was not received. 2 0 1 STM_ENABLED STM_ENABLED Self test mode enabled. 1 STM_DISABLED STM_DISABLED Self test mode disabled. 0 AFM AFM Acceptance filters mode. If this mode is enabled, acceptance filters are used on RX Frames . If disabled, every received frame is stored in the RX buffer. This bit has meaning only if there is at least one filter synthesized. 3 0 1 AFM_ENABLED AFM_ENABLED Acceptance filter mode enabled 1 AFM_DISABLED AFM_DISABLED Acceptance filter mode disabled 0 COMMAND COMMAND Writing logic 1 into each bit gives different command to the IP Core. After writing logic 1, logic 0 does not have to be written. 0 'h5 8 true write-only ABT ABT Abort transmission of CAN frame. CTU CAN FD IP Core will immediately move to the Interframe state. If the Core is a receiver, this command has no effect. Aborting transmission can be used to release the bus immediately. If another unit is receiving frame whose transmission is aborted, it will start transmitting Error frame due to Stuff Error. TXT Buffer will move to TX Error state. 1 0 1 clear RRB RRB Release Receive buffer. This command deletes all data from the Receive buffer and restarts its memory pointers. 2 0 1 clear CDO CDO Clear data overrun flag. This command will clear data overrun flag on RX Buffer. 3 0 1 clear ERCRST ERCRST Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active. 4 0 1 clear RXFCRST Clear RX frames counter. 5 0 1 clear TXFCRST Clear TX frames counter. 6 0 1 clear STATUS STATUS Register signals various states of CTU CAN FD IP Core. Logic 1 signals active status/flag. 0 'h6 8 true read-only RXNE RXNE Receive buffer is not empty. At least one frame is stored in RX Buffer. 0 0 1 TXNF TXNF TXT buffers status. Active if at least one of the TXT Buffers is in "Empty" state. 2 0 1 DOR DOR Data overrun status (flag). A frame was lost due to insufficient space in the Receive buffer. This bit can be cleaned by CDO[RRB] command. 1 0 1 EFT EFT Error frame is beeing transmitted at the moment. 3 0 1 RXS RXS CTU CAN FD IP Core is a receiver of CAN Frame. 4 0 1 TXS TXS CTU CAN FD IP Core is a transmitter of CAN Frame. 5 0 1 EWL EWL Error status. Error warning limit was reached at any of error counters. 6 0 1 IDLE IDLE Bus status. Bus is "idle", the controller is " integrating" or "bus off". Therefore this bit is active when there is no activity on the bus. 7 1 1 SETTINGS SETTINGS This register enables the whole CAN FD Core, configures FD Type, Internal loopback and retransmission options. 0 'h7 8 true read-write RTRLE RTRLE Retransmitt limit enable. If enabled, the core only attempts to transmitt each frame up to RTR_TH times. If not succesfull, the TXT Buffer will end up in "Failed" state. 0 0 1 RTRLE_ENABLED RTRLE_ENABLED Retransmitt limit is enabled. 1 RTRLE_DISABLED RTRLE_DISABLED Retransmitt limit is disabled. 0 RTRTH RTRTH The maximal amount of retransmission attempts. 1 0 4 ILBP ILBP Internal loop-back option (recommended only for testing). If internal loopback options is enabled the Core automatically receive any dominant bit it transmitts. 5 0 1 INT_LOOP_DISABLED INT_LOOP_DISABLED Internal loop-back is disabled. 0 INT_LOOP_ENABLED INT_LOOP_ENABLED Internal loop-back is enabled. 1 ENA ENA Enable bit for the whole CAN FD Controller. When disabled, IP Core acts as if not connected to the CAN Bus. 6 0 1 CTU_CAN_ENABLED CTU_CAN_ENABLED The CAN Core is enabled. 1 CTU_CAN_DISABLED CTU_CAN_DISABLED The CAN Core is disabled. 0 NISOFD NISOFD Selection between two possible CAN FD specifications. This bit should be modified only when SETTINGS[ENA]=0. 7 0 1 ISO_FD ISO_FD The CAN Controller conforms to ISO CAN FD specification. 0 NON_ISO_FD NON_ISO_FD The CAN Controller conforms to NON ISO CAN FD specification. 1 INT_STAT INT_STAT Reading this register returns logic 1 for each interrupt which was captured (interrupt vector). Writing logic 1 to any bit clears according bit of captured interrupt. Writing logic 0 has no effect. 0 'h8 16 true read-writeOnce RXI RXI Frame Received interrupt. Interrupt set has priority over clear. 0 0 1 clear TXI TXI Frame Transmitted sucesfully interrupt. Interrupt set has priority over clear. 1 0 1 clear EWLI EWLI Error warning limit reached interrupt. Interrupt set has priority over clear. 2 0 1 clear DOI DOI Data overrun on RX Buffer Interrupt. Interrupt clear has priority over set. 3 0 1 clear EPI EPI Node became error passive or bus off interrupt. Interrupt set has priority over clear. 4 0 1 clear ALI ALI Arbitration lost Interrupt. Interrupt set has priority over clear. 5 0 1 clear BEI BEI Bus Error interrupt. Interrupt set has priority over clear. 6 0 1 clear LFI LFI Event logging finished interrupt. Interrupt set has priority over clear. 7 0 1 clear RXFI RXFI Receive Buffer full interrupt. Interrupt set has priority over clear. 8 0 1 clear BSI BSI Bit-rate shifted interrupt. Interrupt set has priority over clear. 9 0 1 clear RBNEI RBNEI Receive Buffer not empty Interrupt. Clearing this interrupt and not reading out content of RX Buffer via RX_DATA will re-activate the interrupt. Interrupt set has priority over clear. 10 0 1 clear TXBHCI TXBHCI TX Buffer HW command interrupt. Anytime TX Buffer receives HW command from CAN Core which changes TXT Buffer state to TX Ok, Error or Aborted, this interrupt will be acivated. Interrupt set has priority over clear. 11 0 1 clear RX_SETTINGS RX_SETTINGS Settings register for FIFO RX Buffer. 0 'h62 8 true read-write RTSOP RTSOP Receive buffer Timestamp option. 0 0 1 RTS_END RTS_END Timestamp in on received frame in RX FIFO is captured in the end of the CAN frame (in last bit of EOF field). 0 RTS_BEG RTS_BEG Timestamp in on received frame in RX FIFO is captured in the begining of the CAN frame (in SOF field). 1 INT_ENA_CLR INT_ENA_CLR Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Disabled interrupt wil not affect "int" output of CAN Core event if it is captured in INT_STAT register. 0 'h10 16 true write-only INT_ENA_CLR INT_ENA_CLR Bit meaning is equivalent to register INT_STAT. 0 0 12 clear INT_MASK_CLR INT_MASK_CLR Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. If particular interrupt is un-masked, it will be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI). 0 'h18 16 true write-only INT_MASK_CLR INT_MASK_CLR Bit meaning is equivalent to register INT_STAT. 0 'h0 12 clear INT_MASK_SET INT_MASK_SET Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each masked interrupt. If particular interrupt is masked, it won't be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI). 0 'h14 16 true read-writeOnce INT_MASK_SET INT_MASK_SET Bit meaning is equivalent to register INT_STAT. 0 'h0 12 clear INT_ENA_SET INT_ENA_SET Writing logic 1 to a bit enables according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each enabled interrupt. If interrupt is captured in INT_STAT, enabled interrupt will cause "int" output to be asserted. Interrupts are level-based. To capture interrupt to INT_STAT register, interrupt must be unmasked. 0 'hC 16 true read-writeOnce INT_ENA_SET INT_ENA_SET Bit meaning is equivalent to register INT_STAT. 0 'h0 12 clear BTR_FD BTR_FD Bit timing register for data bit-rate. This register should be modified only when SETTINGS[ENA]=0. 0 'h20 32 true read-write PH2_FD PH2_FD Phase 2 segment 13 3 5 PROP_FD PROP_FD Propagation segment 0 3 6 PH1_FD PH1_FD Phase 1 segment 7 3 5 BRP_FD Baud-rate prescaler 19 4 8 SJW_FD Synchronisation jump width 27 2 5 VERSION VERSION Version register with IP Core version. 0 'h2 16 true read-only VER_MINOR MINOR Minor part of the IP Core version. E.g for version 2.1 this field has value 0x01. 0 8 VER_MAJOR MAJOR Minor part of the IP Core version. E.g for version 2.1 this field has value 0x02. 8 8 BTR BTR Bit timing register for nominal bit-rate. This register should be modified only when SETTINGS[ENA]=0. 0 'h1C 32 true read-write PROP PROP Propagation segment 0 5 7 PH1 PH1 Phase 1 segment 7 3 6 PH2 PH2 Phase 2 segment 13 5 6 BRP Baud-rate prescaler 19 'hA 8 SJW Synchronisation jump width 27 2 5 ALC ALC Arbitration lost capture register. Determines bit position of last arbitration lost. 0 'h75 8 true read-only ALC_BIT ALC_BIT Arbitration lost capture bit position. If ALC_ID_FIELD = ALC_BASE_ID then bit index of BASE identifier in which arbitration was lost is given as: 11 - ALC_VAL. If ALC_ID_FIELD = ALC_EXTENSION then bit index of EXTENDED identifier in which arbitration was lost is given as: 18 - ALC_VAL. For other values of ALC_ID_FIELD, this value is undefined. 0 0 5 ALC_ID_FIELD ALC_ID_FIELD Sub field of CAN Identifier in which arbitration was lost. 5 0 3 ALC_BASE_ID ALC_BASE_ID Arbitration was lost during base identifier. 00 ALC_SRR_RTR ALC_SRR_RTR Arbitration was lost during first bit after Base identifier (SRR of Extended Frame, RTR bit of CAN 2.0 Base Frame) 01 ALC_IDE ALC_IDE Arbitration was lost during IDE bit. 02 ALC_EXTENSION ALC_EXTENSION Arbitration was lost during Identifier extension. 03 ALC_RTR ALC_RTR Arbitration was lost during RTR bit after Identifier extension! 04 EWL EWL Error warning limit register. This register should be modified only when SETTINGS[ENA]=0. 0 'h24 8 true read-write EW_LIMIT EW_LIMIT Error warning limit. If an error warning limit is reached interrupt can be called. Error warning limit indicates heavily disturbed bus. Note that according to CAN specification this value is fixed at 96 and should not be configurable! The configuration of this value is one of the extra features of this IP Core. 0 96 8 ERP ERP Error passive limit register. This register should be modified only when SETTINGS[ENA]=0. 0 'h25 8 true read-write ERP_LIMIT ERP_LIMIT Error passive limit. When one of error counters (RXC/TXC) exceeds this value, i Fault confinement state changes to error passive. Note that according to CAN specification this value is fixed at 128 and should not be configurable! The configuration of this value is one of the extra features of this IP Core. Note that IP Core always turns to bus_off state once any error counter reaches 255! 0 128 8 FAULT_STATE FAULT_STATE Fault confinement state of the node. This state can be manipulated by writes to CTR_PRES register. When these counters are set Fault confinement state changes automatically. 0 'h26 16 true read-only ERP ERP Error passive 1 0 1 BOF BOF Bus off 2 0 1 ERA ERA Error active 0 1 1 FILTER_A_VAL FILTER_A_VAL Bit value for acceptance filters. Filters A, B, C are available. The identifier format is the same as transmitted and received identifier format. BASE Identifier is 11 LSB and Identifier extension are bits 28-12! Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtX=false";. If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_09846e1a_b03a_4f0b_99b5_c1981400ea9e 0 'h38 32 true read-write BIT_VAL_A_VAL BIT_VAL_A_VAL Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_A_MASK register are compared. 0 0 29 FILTER_STATUS FILTER_STATUS This register provides information if the Core is synthesized with fillter support. 0 'h56 16 true read-only SFA SUP_FILTA Logic 1 when the Core was synthesized with "sup_filtA = true" Otherwise logic 0. 0 1 SFB SUP_FILTB Logic 1 when the Core was synthesized with "sup_filtB = true" Otherwise logic 0. 1 1 SFR SUP_RANGE Logic 1 when the Core was synthesized with "sup_range = true" Otherwise logic 0. 3 1 SFC SUP_FILTC Logic 1 when the Core was synthesized with "sup_filtC = true" Otherwise is logic 0. 2 1 TX_PRIORITY TX_PRIORITY Priority of the TXT Buffers in TX Arbitrator. Higher priority value signals that buffer is selected earlier for transmission. If two buffers have equal priorities, the one with lower index is selected. 0 'h70 16 true read-write TXT1P TXT1P Priority of TXT Buffer 1. 0 1 3 TXT2P TXT2P Priority of TXT Buffer 2. 4 0 3 TXT3P TXT3P Priority of TXT Buffer 3. 8 0 3 TXT4P TXT4P Priority of TXT Buffer 4. 12 0 3 TX_COMMAND TX_COMMAND Command register for TXT Buffers. Command is activated by setting TXC(E,R,A) bit to logic 1. Buffer that receives the command is selected by setting bit TXBI(1..4) to logic 1. Command and index must be set by single access. Register is automatically erased upon the command completion and 0 does not need to be written. Reffer to description of TXT Buffer circuit for TXT buffer State machine. If TXCE and TXCR are applied simultaneously, only TXCE command is applied. If multiple commands are applied, only those which have effect in immediate state of the buffer are applied on a buffer. 0 'h6C 16 true write-only TXCE TXCE Activates "set_empty" command. Transits frone TX Done, TX Error or TX Aborted to Done. Does not have any effect in other states. 0 0 1 clear TXCR TXCR Activates "set_ready" command. Transits frone TX Done, TX Error, TX Aborted or Empty to Ready. Does not have any effect in other states. 1 0 1 clear TXCA TXCA Activates "set_abort" command. Transits from Ready to TX Aborted. If transmission is in progress (state TX in Progress) from the buffer, transits to TX Aborted if current transmission is not succesfull. If the transmission is sucesfull, it has no effect. Does not have any effect in other states. 2 0 1 clear TXB1 TXB1 Command is applied on TXT Buffer 1. 8 0 1 clear TXB2 TXB2 Command is applied on TXT Buffer 2. 9 0 1 clear TXB3 TXB3 Command is applied on TXT Buffer 3. 10 0 1 clear TXB4 TXB4 Command is applied on TXT Buffer 4. 11 0 1 clear TIMESTAMP_HIGH TIMESTAMP_HIGH Register with mirrored values of timestamp input. Bits 63:32 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH. 0 'h94 32 true read-only TIMESTAMP_HIGH TIMESTAMP_HIGH Bits 63:32 of timestamp input. 0 00 32 read-only TIMESTAMP_LOW TIMESTAMP_LOW Register with mirrored values of timestamp input. Bits 31:0 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH. 0 'h90 32 true read-only TIMESTAMP_LOW TIMESTAMP_LOW Bits 31:0 of timestamp input. 0 0 32 read-only YOLO_REG YOLO_REG Register for fun :) 0 'h88 32 true read-only YOLO_VAL What else could be in this register?? 0 'hDEADBEEF 32 SSP_CFG Configuration of Secondary sampling point which is used for Transmitter in Data Bit-Rate. This register should be modified only when SETTINGS[ENA]=0. 0 'h7A 16 true read-write SSP_OFFSET Secondary sampling point offset. 0 0 7 SSP_SRC Source of secondary sampling point delay. Measured in clock cycles, not Time quanta! Sampling point is delayed from regular sampling point by a value configured by this register. If configured value exceeds 130, it is saturated on 130. Thus maximal possible delay is 130 clk_sys clock cycles. 8 0 2 SSP_SRC_MEASURED TRV_SRC_MEASURED Use measured value (also available in TRV_DELAY). 0 SSP_SRC_OFFSET TRV_SRC_OFFSET Use SSP_OFFSET value. 2 SSP_SRC_MEAS_N_OFFSET TRV_SRC_MEAS_N_OFFSET Use measured value (available in TRV_DELAY) + SSP_OFFSET. 1 DEBUG_REGISTER DEBUG_REGISTER Register for reading out state of the controller. This register is only for debugging purposes! 0 'h84 32 true read-only STUFF_COUNT Actual stuff count modulo 8 as definned in ISO FD protocol. Stuff count is erased in the beginning of the frame and increased by one with each stuff bit until STUFF count field in ISO FD CRC. Then it stays fixed until the beginning of next frame. In non-ISO FD or normal CAN stuff bits are counted until the end of a frame. Note that this field is NOT gray encoded as defined in ISO FD standard. Stuff count is calculated only as long as controller is transceiving on the bus. During the reception this value remains fixed! 0 0 3 DESTUFF_COUNT Actual de-stuff count modulo 8 as defined in ISO FD protocol. De-Stuff count is erased in the beginning of the frame and increased by one with each de-stuffed bit until STUFF count field in ISO FD CRC. Then it stays fixed until beginning of next frame. In non-ISO FD or normal CAN de-stuff bits are counted until the end of the frame. Note that this field is NOT grey encoded as defined in ISO FD standard. De-stuff count is calculated in both. Transceiver as well as receiver. 3 0 3 PC_ARB Protocol control State machine is in Arbitration field. 6 0 1 PC_CON Protocol control State machine is in Control field. 7 0 1 PC_DAT Protocol control State machine is in Data field. 8 0 1 PC_CRC Protocol control State machine is in CRC field. 9 0 1 PC_EOF Protocol control State machine is in End of file field. 10 0 1 PC_OVR Protocol control State machine is in Overload field. 11 0 1 PC_INT Protocol control State machine is in Interrupt field. 12 0 1 TX_COUNTER TX_COUNTER Counter for transmitted frames to enable bus traffic measurement. 0 'h80 32 true read-only TX_COUNTER_VAL Counter for transcieved frames to enable bus traffic measurement. 0 0 32 RX_COUNTER RX_COUNTER Counter for received frames to enable bus traffic measurement 0 'h7C 32 true read-only RX_COUNTER_VAL Counter for received frames to enable bus traffic measurement 0 0 32 ERR_CAPT ERR_CAPT Last error frame capture. 0 'h74 8 true read-only ERR_POS ERR_POS Position of the last error. 0 'h1F 5 ERC_POS_SOF ERC_POS_SOF Error in Start of Frame 0 ERC_POS_ARB ERC_POS_ARB Error in Arbitration Filed 1 ERC_POS_ERR ERC_POS_ERR Error during Error frame 7 ERC_POS_OVRL ERC_POS_OVRL Error in Overload frame 8 ERC_POS_CTRL ERC_POS_CTRL Error in Control field 2 ERC_POS_OTHER ERC_POS_OTHER Other position of error 'h1F ERC_POS_DATA ERC_POS_DATA Error in Data Field 3 ERC_POS_CRC ERC_POS_CRC Error in CRC Field 4 ERC_POS_INTF ERC_POS_INTF Error in interframe space 6 ERC_POS_ACK ERC_POS_ACK Error in Acknowledge field or CRC delimiter 5 ERR_TYPE ERR_TYPE Type of the last error 5 0 3 ERC_BIT_ERR ERC_BIT_ERR Bit Error 0 ERC_CRC_ERR ERC_CRC_ERR CRC Error 1 ERC_FRM_ERR ERC_FRM_ERR Form Error 2 ERC_ACK_ERR ERC_ACK_ERR Acknowledge Error 3 ERC_STUF_ERR ERC_STUF_ERR Stuff Error 4 TX_STATUS TX_STATUS Status of TXT Buffers. 0 'h68 16 true read-only TX2S TX1S Status of TXT Buffer 2. Bit field meaning is analogous to TX1S. 4 'h8 4 TX1S TX2S Status of TXT Buffer 1. 0 'h8 4 TXT_ETY TXT_EMPTY TXT Buffer is empty. 'h8 TXT_TOK TXT_OK Transmission from TXT Buffer finished OK. 'h4 TXT_ERR TXT_ERR Transmission from TXT Buffer failed. 'h6 TXT_ABT TXT_ABT Transmission from TXT Buffer was aborted by SW. 'h7 TXT_TRAN TXT_TRAN Transmission from TXT Buffer is in progress. 'h2 TXT_ABTP TXT_ABTP Transmission from TXT Buffer is in progress, stop trying at nearest error frame or arbitration lost. 'h3 TXT_RDY TXT_RDY TXT Buffer is ready to be selected for transmission by the CAN Core. 'h1 TX3S Status of TXT Buffer 3. Bit field meaning is analogous to TX1S. 8 'h8 4 TX4S Status of TXT Buffer 4. Bit field meaning is analogous to TX1S. 12 'h8 4 TRV_DELAY TRV_DELAY 0 'h78 16 true read-only TRV_DELAY_VALUE TRV_DELAY_VALUE When sending CAN FD Frame with bit rate shift, transceiver delay is measured. After the measurement (after EDL bit), it can be read out from this register. The value in this register is valid since first transmission of CAN FD frame with bit rate shift. After each next measurement the value is updated. This register can be used for transceiver TXD to RXD delay verifcation. 0 0 16 RX_DATA RX_DATA Read data word from RX Buffer. 0 'h64 32 true read-only RX_DATA RX_DATA The recieve buffer data at read pointer position in FIFO. CAN Frame layout in RX buffer is described in Figure 7. By reading data from this register read_pointer is automatically increased, as long as there is next data word stored in the buffer. Next Read from this register returns next word of CAN frame. First stored word in the buffer is FRAME_FORM, next TIMESTAMP_U etc. In detail bits of each word have following meaning. If any access is executed (8 bit, 16 bit or 32 bit), the read_pointer automatically increases. It is recomended to use 32 bit acccess on this register. 0 0 32 modify RX_POINTERS RX_POINTERS Pointers in the RX FIFO buffer for read (by SW) and write (by Protocol control FSM). 0 'h5C 32 true read-only RX_WPP RX_WP Write pointer position in Receive buffer. During store of received frame write pointer is updated. 0 0 12 RX_RPP RX_RPP Read pointer position in Receive buffer. During read of received frame read pointer is updated. 16 0 12 RX_MEM_INFO RX_MEM_INFO Information register about FIFO memory of RX Buffer. 0 'h58 32 true read-only RX_BUFF_SIZE RX_BUFF_SIZE_VALUE Size of th Receive buffer. This parameter is configurable before synthesis. 0 13 RX_MEM_FREE RX_MEM_FREE Number of free 32 bit words in the RX Buffer. 16 13 RX_STATUS RX_STATUS Information register one about FIFO Receive buffer. 0 'h60 16 true read-only RXE RXE Receive Buffer is empty. There is no CAN Frame stored in it. 0 1 1 RXF RXF Receive Buffer is full. 1 1 1 RXFRC RXFRC Receive Buffer frame count. Number of CAN Frames stored in the RX Buffer. 4 0 11 FILTER_CONTROL FILTER_CONTROL Every filter can be configured to accept only selected frame types. Every bit is active in logic 1. 0 'h54 16 true read-write FANB FILT_A_BASIC CAN Basic Frame should be accepted by filter A. 0 1 1 FAFB FILT_A_FD_BAS CAN FD Basic Frame should be accepted by filter A. 2 1 1 FANE FILT_A_EXT CAN Extended Frame should be accepted by Filter A. 1 1 1 FAFE FILT_A_FD_EXT CAN FD Extended Frame should be accepted by filter A. 3 1 1 FBNB FILT_B_BASIC CAN Basic Frame should be accepted by filter B. 4 0 1 FBNE FILT_B_EXT CAN Extended Frame should be accepted by Filter B. 5 0 1 FBFB FILT_B_FD_BAS CAN FD Basic Frame should be accepted by filter B. 6 0 1 FBFE FILT_B_FD_EXT CAN FD Extended Frame should be accepted by filter B. 7 0 1 FCNB FILT_C_BASIC CAN Basic Frame should be accepted by filter C. 8 0 1 FCNE FILT_C_EXT CAN Extended Frame should be accepted by Filter C. 9 0 1 FCFB FILT_C_FD_BAS CAN FD Basic Frame should be accepted by filter C. 10 0 1 FRFE FILT_RANGE_FD_EXT CAN FD Extended Frame should be accepted by Range filter. 15 0 1 FRFB FILT_RANGE_FD_BAS CAN FD Basic Frame should be accepted by Range filter. 14 0 1 FRNE FILT_RANGE_EXT CAN Extended Frame should be accepted by Range filter. 13 0 1 FRNB FILT_RANGE_BASIC CAN Basic Frame should be accepted by Range filter. 12 0 1 FCFE FILT_C_FD_EXT CAN FD Extended Frame should be accepted by filter C. 11 0 1 FILTER_RAN_HIGH FILTER_RAN_HIGH High Identifier threshold for range filter. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_range=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_41f98f04_041f_4ab6_b60d_c6226cd54eb6 0 'h50 32 true read-write BIT_RAN_HIGH_VAL BIT_RAN_HIGH_VAL High threshold value 0 0 29 FILTER_RAN_LOW FILTER_RAN_LOW Low Identifier threshold for range filter. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_range=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_41f98f04_041f_4ab6_b60d_c6226cd54eb6 0 'h4C 32 true read-write BIT_RAN_LOW_VAL BIT_RAN_LOW_VAL Low threshold value 0 0 29 FILTER_C_VAL FILTER_C_VAL Bit value for acceptance filter C. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtC=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_d4ccabd1_3f50_49b0_ae1e_45cf5fdb460e 0 'h48 32 true read-write BIT_VAL_C_VAL BIT_VAL_C_VAL Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_C_MASK register are compared. 0 0 29 FILTER_C_MASK FILTER_C_MASK Bit mask for acceptance filter C. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtC=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_d4ccabd1_3f50_49b0_ae1e_45cf5fdb460e 0 'h44 32 true read-write BIT_MASK_C_VAL BIT_MASK_C_VAL Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_C_VALUE. Logic 0 indicates this bit is not compared. 0 0 29 FILTER_B_VAL FILTER_B_VAL Bit value for acceptance filter B. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtB=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_ee0c8305_bed6_412e_8743_8e3657e8b866 0 'h40 32 true read-write BIT_VAL_B_VAL BIT_VAL_B_VAL Bit Value for acceptance filters to be compared with income identifier. Only bits set in according to FILTER_B_MASK register are compared. 0 0 29 FILTER_B_MASK FILTER_B_MASK Bit mask for acceptance filter B. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtB=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_ee0c8305_bed6_412e_8743_8e3657e8b866 0 'h3C 32 true read-write BIT_MASK_B_VAL BIT_MASK_B_VAL Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_B_VALUE. Logic 0 indicates this bit is not compared. 0 0 29 FILTER_A_MASK FILTER_A_MASK Bit mask for acceptance filter A. The identifier format is the same as transmitted and received identifier format. BASE Identifier is in bits 28 : 18 and Identifier extension are bits 17 : 0. Note that filter support is available by default but it can be left out from synthesis (to save logic) by setting "sup_filtA=false". If the particular filter is not supported, writes to this register have no effect and read will return all zeroes. uuid_09846e1a_b03a_4f0b_99b5_c1981400ea9e 0 'h34 32 true read-write BIT_MASK_A_VAL BIT_MASK_A_VAL Bit mask for acceptance filters. Logic 1 indicates this bit of Income identifier is compared with the same bit in FILTER_A_VALUE. Logic 0 indicates this bit is not compared. 0 0 29 CTR_PRES CTR_PRES Register for manipulation with error counters. 0 'h30 32 true write-only CTPV CTPV Counter value to set. 0 0 9 clear PTX PTX Preset value from CTR_PRES_VAL to TX Error counter. 9 0 1 clear PRX PRX Preset value fromCTR_PRES_VAL to RX Error counter. 10 0 1 clear ENORM ENORM Erase Nominal bit time error counter. 11 0 1 clear EFD EFD Erase Data bit time error counter. 12 0 1 clear ERR_FD ERR_FD 0 'h2E 16 true read-only ERR_FD_VAL ERR_FD_VAL Number of errors in the Data bit time. 0 0 16 ERR_NORM ERR_NORM 0 'h2C 16 true read-only ERR_NORM_VAL ERR_NORM_VAL Number of errors in the Nominal bit time. 0 0 16 TXC TXC Counter for transcieved frames. 0 'h2A 16 true read-only TXC_VAL Counter for transcieved frames to enable bus traffic measurement. 0 0 16 RXC RXC Counter for received frames. 0 'h28 16 true read-only RXC_VAL RXC_VAL Receive error counter. This register determines Fault confiment state (Error active, Error passive, Bus off) according to CAN specification. 0 0 16 read-only TX_Buffer_1 TXT Buffer 1 Access to this memory region is mapped to TXT Buffer 1. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB1_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB1_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB1_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access. 'h100 256 32 memory true TXTB1_DATA_1 TX_DATA_1 This adress word corresponds to FRAME_FORM word 0 'h0 32 TXTB1_DATA_1 0 32 TXTB1_DATA_2 TX_DATA_2 This adress word corresponds to IDENTIFIER word. 0 'h4 32 TXTB1_DATA_2 0 32 TXTB1_DATA_20 TX_DATA_20 This adress word corresponds to DATA_61_64 word. 0 'h4C 32 TXTB1_DATA_20 0 32 TX_Buffer_2 TXT Buffer 2 Access to this memory region is mapped to TXT Buffer 2. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB2_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB2_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB2_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access. 'h200 256 32 memory true TXTB2_DATA_1 This adress word corresponds to FRAME_FORM word 0 'h0 32 TXTB2_DATA_1 0 32 TXTB2_DATA_2 This adress word corresponds to IDENTIFIER word. 0 'h4 32 TXTB2_DATA_2 0 32 TXTB2_DATA_20 This adress word corresponds to DATA_61_64 word. 0 'h4C 32 TXTB2_DATA_20 0 32 TX_Buffer_3 TXT Buffer 3 Access to this memory region is mapped to TXT Buffer 3. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB3_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB3_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB2_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access. 'h300 256 32 memory true TXTB3_DATA_1 This adress word corresponds to FRAME_FORM word 0 'h0 32 TXTB3_DATA_1 0 32 TXTB3_DATA_2 This adress word corresponds to IDENTIFIER word. 0 'h4 32 TXTB3_DATA_2 0 32 TXTB3_DATA_20 This adress word corresponds to DATA_61_64 word. 0 'h4C 32 TXTB3_DATA_20 0 32 TX_Buffer_4 TXT Buffer 4 Access to this memory region is mapped to TXT Buffer 4. CAN FD frame for transmittion can be inserted to this buffer. The frame layout corresponds to the layout described in Chapter "CAN FD frame format". First adress in this region (TXTB4_DATA_1) corresponds to FRAME_FORMAT_W, second address (TXTB4_DATA_2) corresponds to IDENTIFIER_W etc. The last address (TXTB4_DATA_20) corresponds to DATA_61_64_W. The adresses in between correspond linearly. This memory region is write only and read access will return all zeroes. This region supports only 32 bit access. 'h400 256 32 memory true TXTB4_DATA_1 This adress word corresponds to FRAME_FORM word 0 'h0 32 TXTB4_DATA_1 0 32 TXTB4_DATA_2 This adress word corresponds to IDENTIFIER word. 0 'h4 32 TXTB4_DATA_2 0 32 TXTB4_DATA_20 This adress word corresponds to DATA_61_64 word. 0 'h4C 32 TXTB4_DATA_20 0 32 Event_Logger Event Logger Registers for control of Event logger and memory access to event logger RAM. Accessible only when event logger is synthesized. 'h500 256 32 register true LOG_TRIG_CONFIG LOG_TRIG_CONFIG Register for configuration of event logging triggering conditions. If Event logger is in Ready state and any of triggering conditions appear it starts recording the events on the bus (moves to Running state). Logic 1 in each bit means this triggering condition is valid. 0 'h0 32 read-write T_SOF Trigger on Start of frame field appears 0 0 1 T_ARBL Trigger on arbitration was lost 1 0 1 T_REV Trigger on valid frame received 2 0 1 T_TRV Trigger on valid frame transmitted. 3 0 1 T_OVL Trigger when Overload frame is transmitted 4 0 1 T_RES Trigger when the unit starts receiving a new frame 17 0 1 T_ERR Trigger on error appeared 5 0 1 T_BRS Trigger when bit rate is shifted 6 0 1 T_USRW When logic 1 is written into this bit event logging is triggered immediately 7 0 1 T_ARBS Trigger on Arbitration field starts 8 0 1 T_CTRS Trigger on Control field starts 9 0 1 T_ACKNR Trigger on acknowledge not received in ACK slot 13 0 1 T_EWLR Trigger on Error warning limit reached 14 0 1 T_ERPC Trigger on Fault confinement state changed 15 0 1 T_DATS Trigger on Data field starts 10 0 1 T_ACKR Trigger on acknowledge received in ACK slot 12 0 1 T_TRS Trigger when the unit starts transmitting a new frame. 16 0 1 T_CRCS Trigger on CRC field starts 11 0 1 LOG_CAPT_CONFIG LOG_CAPT_CONFIG Register for configuring which events to capture by event logger into the logger FIFO memory when event logger is running. 0 'h4 32 read-write C_SOF Capture when Start of frame field appears. 0 0 1 C_ARBL Capture when arbitration was lost. 1 0 1 C_REV Capture when valid frame received. 2 0 1 C_TRV Capture when valid frame transmitted. 3 0 1 C_OVL Capture when overload appeared. 4 0 1 C_ERR Capture when error appeared. 5 0 1 C_BRS Capture when bit rate is shifted. 6 0 1 C_ARBS Capture when Arbitration field is started. 7 0 1 C_SYNE Capture when synchronization edge was detected (recessive to dominant edge). 17 0 1 C_STUFF Capture when Stuff bit was inserted (transceiver only, one fixed stuf bit before CRC sequence is not captured) 18 0 1 C_CTRS Capture when Control field starts. 8 0 1 C_DESTUFF Capture when received bit is de-stuffed (receiver and transceiver, one fixed stuff bit before CRC sequence is not captured). 19 0 1 C_DATS Capture when Data field starts. 9 0 1 C_TRS Capture when the unit starts transmitting 15 0 1 C_RES Capture when receive of frame started. 16 0 1 C_OVR Capture data overrun 20 0 1 C_CRCS Capture when CRC field starts. 10 0 1 C_ACKR Capture when Acknowledge was received in ACK Slot. 11 0 1 C_ACKNR Capture when Acknowledge was not received in ACK Slot. 12 0 1 C_EWLR Capture when Error warning limit is reached. 13 0 1 C_ERC Capture when Fault confinement state is changed. 14 0 1 LOG_STATUS LOG_STATUS Status register for Event logger. 0 'h8 16 read-only LOG_CFG Event logger is in Config state 0 1 1 LOG_RDY Event logger is in Ready state 1 0 1 LOG_RUN Event logger is in Running state 2 0 1 LOG_EXIST Information whether event logger is synthesized in the circuit. 7 1 LOG_SIZE Size of event logger. This information is valid only if logger is synthesized! (generic "use_logger") 8 8 LOG_POINTERS LOG_POINTERS Pointers to Logger RAM memory. 0 'hA 16 read-only LOG_WPP Write pointer from Event Logging FSM. 0 0 8 LOG_RPP Read pointer for user access. 8 0 8 LOG_COMMAND LOG_COMMAND Register for controlling the state machine of Event logger and read pointer position. Every bit is active in logic 1. 0 'hC 8 write-only LOG_STR Start event logging. Move from Config State to Ready state. Has no effect in Ready state or Running state. 0 0 1 clear LOG_ABT Abort event logging. Move from Ready State or Running State to Config State. 1 0 1 clear LOG_UP Move read pointer one position up. 2 0 1 clear LOG_DOWN Move read pointer one position down. 3 0 1 clear LOG_CAPT_EVENT_2 LOG_CAPT_EVENT_2 Second word of the captured event at read pointer position. 0 'h14 32 read-only EVNT_TYPE EVNT_TYPE Type of captured event. 0 0 5 DSTF_EVNT DSTF_EVNT Bit was destuffed. 'h14 SE_EVNT SE_EVNT Synchronization edge appeared. 'h12 RS_EVNT RS_EVNT Frame reception has started. 'h11 DOR_EVNT DOR_EVNT Data overrun appeared. 'h15 STF_EVNT STF_EVNT Bit was stuffed. 'h13 SOF_EVNT SOF_EVNT Start of frame field has started. 'h1 ARBL_EVNT ARBL_EVNT Arbitration was lost. 'h2 FREC_EVNT FREC_EVNT Frame reception ended succesfully. 'h3 TRANV_EVNT TRAN_EVNT Frame transmission ended succesfully. 'h4 OVRL_EVNT OVRL_EVNT Overload frame transmission started. 'h5 ERR_EVNT ERR_EVNT Error frame transmission started. 'h6 BRS_EVNT BRS_EVNT Bit rate was shifted. 'h7 FCSC_EVNT FCSC_EVNT Fault confinement state has changed. (Error active to error passive, or error passive to bus-off). 'hF CRCS_EVNT CRCS_EVNT CRC field has started. 'hB TS_EVNT TS_EVNT Frame transmission has started. 'h10 ACKR_EVNT ACKR_EVNT Acknowledge was received in ACK bit. 'hC ACKN_EVNT ACKN_EVNT Acknowledge was not received in ACK bit. 'hD ARBS_EVNT ARBS_EVNT Arbitration field has started. 'h8 CONS_EVNT CONS_EVNT Control field has started. 'h9 EWLR_EVNT EWLR_EVNT Error warning limit was reached. 'hE DATS_EVNT DATS_EVNT Data field has started. 'hA EVNT_DEN EVNT_DEN Numerical details of given event. This field captures states of stuffing or destuffing counters when type of recorded event is STF_EVNT or DSTF_EVNT. 5 0 3 EVNT_DET EVNT_DET Details of recorded event. Event details depend on type of the event in EVNT_TYPE. 8 0 5 FRM_ERR FRM_ERR If event type is ERR_EVNT and form error ocurred. 'h10 ACK_ERR ACK_ERR If event type is ERR_EVNT and ack error ocurred. 'h8 CRC_ERR CRC_ERR If event type is ERR_EVNT and crc error ocurred. 'h4 ST_ERR ST_ERR If event type is ERR_EVNT and stuff error ocurred. 'h2 BIT_ERR BIT_ERR If event type is ERR_EVNT and bit error ocurred. 'h1 S_UP S_UP If event type is BRS_EVNT and bit rate was shifted from Nominal to Data. 'h1 S_DOWN S_DOWN If event type is BRS_EVNT and bit rate was shifted from Data to Nominal. 'h2 IS_SYNC IS_SYNC If event type is SE_EVNT and synchronisation edge arrived in SYNC field. 'h1 IS_PROP IS_PROP If event type is SE_EVNT and synchronisation edge arrived in PROP field. 'h2 IS_FDSTF IS_FDSTF If event type is DSTF_EVNT and de-stuffed bit is "fixed". 'h1 ISN_FDSTF ISN_FDSTF If event type is DSTF_EVNT and de-stuffed bit is normal de-stuffed bit. 'h0 IS_PH1 IS_PH1 If event type is SE_EVNT and synchronisation edge arrived in PH1 field. 'h4 ISN_FSTF ISN_FSTF If event type is STF_EVNT and stuffed bit is normal stuffed bit. 'h0 IS_FSTF IS_FSTF If event type is STF_EVNT and stuffed bit is "fixed". 'h1 IS_PH2 IS_PH2 If event type is SE_EVNT and synchronisation edge arrived in PH2 field. 'h8 EVNT_DEA Additional details of recorded event. 13 0 3 RE_SNC RE_SNC If event type is SE_EVNT and synchronisation edge appeared during resynchronisation. 'h2 NO_SNC NO_SNC If event type is SE_EVNT and synchronisation edge appeared no synchronisation. 'h0 HA_SNC HA_SNC If event type is SE_EVNT and synchronisation edge appeared hard synchronisation. 'h1 EVENT_TS_15_0 EVENT_TS_15_0 Lowest 16 bits of timestamp at the time when event occured. 16 0 16 LOG_CAPT_EVENT_1 LOG_CAPT_EVENT_1 First word of the captured event at read pointer position. 0 'h10 32 read-only EVENT_TS_48_16 Bits 48 to 16 of timestamp at the time when the event occured. 0 0 32 8 CAN_Frame_format CAN FD frame format CAN Frame format describtion in as it is stored in TXT Buffers and RX Buffer. CAN_FD_Frame_format CAN FD Frame format 'h0 80 32 FRAME_FORM_W FRAME_FORM_W Frame format word with CAN frame metadata. 0 'h0 32 DLC DLC Data length code as defined in CAN FD Specification. 0 4 RTR RTR Remote transmission request flag. Has meaning only for CAN frames. CAN FD does not have RTR frames. 5 1 RTR_FRAME RTR_FRAME CAN frame is RTR frame. 1 NO_RTR_FRAME NO_RTR_FRAME CAN frame is not RTR frame. 0 IDE IDE Extended Identifier type. Distinguishes between Base and Extended Identifiers. 6 1 BASE BASE Frame Identifier is Basic (11 bits) 0 EXTENDED EXTENDED Frame Identifier is Extended (11 + 18 bits) 1 FDF FDF Frame type. Distinguishes between CAN and CAN FD Frames. 7 1 NORMAL_CAN NORMAL_CAN Frame is CAN frame. 0 FD_CAN FD_CAN Frame is CAN FD frame. 1 TBF TBF Time base format. Should be always set to 1. 8 1 TIME_BASED TIME_BASED TIMESTAMP_L and TIMESTAMP_H contain valid timestamp for transmission or reception. 1 NOT_TIME_BASED NOT_TIME_BASED TIMESTAMP_L and TIMESTAMP_H does not contain valid timestamp for transmission or reception. 0 BRS BRS Bit rate shift. In case of CAN FD frames indicates whether Bit-rate should be shifted during Data phase. This bit has no meaning for CAN Frames. 9 1 BR_SHIFT BR_SHIFT Bit rate should be shifted if frame is CAN FD frame. 1 BR_NO_SHIFT BR_NO_SHIFT Bit rate should not be shifted if frame is CAN FD frame. 0 ESI_RSV ESI_RSV Error state indicator bit for received CAN FD frames. Bit has no meaning for CAN frames nor for transmitted CAN FD frames. 10 1 ESI_ERR_ACTIVE ESI_ERR_ACTIVE Transmitted of received CAN FD frame is error active. 0 ESI_ERR_PASIVE ESI_ERR_PASSIVE Transmitted of received CAN FD frame is error passive. 1 RWCNT RWCNT Size of the CAN frame in RX Buffer without FRAME_FORMAT WORD.(E.g RTR frame RWCNT=3, 64 Byte FD frame RWCNT=19). In TXT Buffer this field has no meaning. 11 5 IDENTIFIER_W IDENTIFIER_W CAN Identifier 0 'h4 32 IDENTIFIER_BASE Base Identifier of CAN frame 18 11 IDENTIFIER_EXT Extended Identifier of CAN frame. Has meaning only if ID_TYPE of FRAME_FORMAT_W is EXTENDED. 0 18 TIMESTAMP_L_W TIMESTAMP_L_W 0 'h8 32 TIME_STAMP_31_0 TIME_STAMP_31_0 Lower 32 bits of timestamp when the frame should be transmitted or when it was received. 0 32 TIMESTAMP_U_W TIMESTAMP_U_W 0 'hC 32 TIMESTAMP_L_W TIMESTAMP_L_W Upper 32 bits of timestamp when the frame should be transmitted or when it was received. 0 32 DATA_1_4_W DATA_1_4_W 0 'h10 32 DATA_1 Data byte 1 of CAN Frame. 0 8 DATA_2 Data byte 2 of CAN Frame. 8 8 DATA_3 Data byte 3 of CAN Frame. 16 8 DATA_4 Data byte 4 of CAN Frame. 24 8 DATA_61_64_W DATA_61_64_W 0 'h4C 32 DATA_61 Data byte 61 of CAN Frame. 0 8 DATA_62 Data byte 62 of CAN Frame. 8 8 DATA_63 Data byte 63 of CAN Frame. 16 8 DATA_64 Data byte 64 of CAN Frame. 24 8 DATA_5_8_W DATA_5_8_W 0 'h14 32 DATA_5 Data byte 5 of CAN Frame. 0 8 DATA_6 Data byte 6 of CAN Frame. 8 8 DATA_7 Data byte 7 of CAN Frame. 16 8 DATA_8 Data byte 8 of CAN Frame. 24 8 8 CAN FD IP Core from Ondrej Ille written at Czech Technical University, department of Measurement. sup_filt_A sup_filt_A 1 sup_range sup_range 1 sup_filt_C sup_filt_C 1 sup_filt_B sup_filt_B 1 Ondrej Ille 3,5,0,0 IP HW Mutable MIT