Skip to content
GitLab
Explore
Sign in
canbus
CTU CAN FD IP Core
Merge requests
Open
0
Merged
436
Closed
60
All
496
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Title
Adapt canbench-sw and CTU_CAN_FD Vivado component to match sources after 207-design-decoupling merge
!180
· created
Jan 05, 2019
by
Pavel Pisa
Merged
0
updated
Jan 05, 2019
add docker script to setup testing environment
!139
· created
Aug 31, 2018
by
Martin Jeřábek
Merged
0
updated
Aug 31, 2018
Added bit-rate switch compensation of Ph2 segment
!13
· created
Dec 12, 2017
by
Ille, Ondrej, Ing.
Bug fixing
Merged
0
updated
Dec 12, 2017
added bounds to ID_dec
!459
· created
Aug 26, 2021
by
Jan Sobotka
Merged
0
updated
Aug 26, 2021
Added byte enable support
!18
· created
Dec 20, 2017
by
Ille, Ondrej, Ing.
Merged
0
updated
Dec 20, 2017
Added explicit warning to register descriptions. Some registers are
!185
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
4
updated
Jan 06, 2019
Added Inferred RAM wrapper to TXT Buffers.
!169
· created
Oct 31, 2018
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Oct 31, 2018
Added Readme to the repo
!6
· created
Dec 06, 2017
by
Ille, Ondrej, Ing.
Merged
0
updated
Dec 06, 2017
add endian_swap to vivado component
!87
· created
Jun 02, 2018
by
Martin Jeřábek
Merged
0
updated
Jun 02, 2018
add reduce_lib.vhd to vivado component file
!142
· created
Sep 02, 2018
by
Martin Jeřábek
Merged
0
updated
Sep 02, 2018
Allow for test randomization in testfw
!110
· created
Jun 18, 2018
by
Martin Jeřábek
Merged
0
updated
Jun 19, 2018
apb_ifc: assert rden for only one cycle; enable psl assertions
!161
· created
Sep 28, 2018
by
Martin Jeřábek
Merged
0
updated
Sep 28, 2018
Automation of Core resource evaluation
!17
· created
Dec 20, 2017
by
Ille, Ondrej, Ing.
FPGA resource optimization
Merged
0
updated
Dec 20, 2017
AXI wrapper and Vivado component
!61
· created
Apr 24, 2018
by
Martin Jeřábek
Xilinx AXI wrapper
Merged
0
updated
Apr 24, 2018
Changed license header of the project to MIT license
!11
· created
Dec 11, 2017
by
Ille, Ondrej, Ing.
Merged
0
updated
Dec 11, 2017
ci: Add driver build to CI script.
!259
· created
Oct 06, 2019
by
Ille, Ondrej, Ing.
Merged
0
updated
Oct 06, 2019
ci: add -R switch to documentation copy
!262
· created
Oct 06, 2019
by
Ille, Ondrej, Ing.
Merged
0
updated
Oct 06, 2019
ci: Add system architecture to pages.
!255
· created
Sep 26, 2019
by
Ille, Ondrej, Ing.
Merged
0
updated
Sep 26, 2019
ci: Add trigger of external job.
!476
· created
Oct 31, 2021
by
Ille, Ondrej, Ing.
Release 2.5
Merged
0
updated
Oct 31, 2021
ci: Adjust path to SLF
!496
· created
Sep 28, 2023
by
Ille, Ondrej, Ing.
Merged
0
updated
Sep 28, 2023
Prev
1
2
3
4
5
…
22
Next