Skip to content
GitLab
Explore
Sign in
canbus
CTU CAN FD IP Core
Merge requests
Open
0
Merged
436
Closed
60
All
496
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Milestone due date
vivado: update component.xml
!208
· created
Jan 21, 2019
by
Martin Jeřábek
Wishlist
Merged
0
updated
Jan 21, 2019
driver: Add timestamp read-out function.
!207
· created
Jan 20, 2019
by
Ille, Ondrej, Ing.
Linux driver
Merged
4
updated
Jan 20, 2019
design: add endian swapper module.
!206
· created
Jan 20, 2019
by
Ille, Ondrej, Ing.
Wishlist
Merged
2
updated
Jan 21, 2019
Resolve "Create basic test library"
!205
· created
Jan 19, 2019
by
Ille, Ondrej, Ing.
Test improvements
Merged
0
updated
Jan 19, 2019
design: replace tx_data shift reg with fifo cache.
!202
· created
Jan 18, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 18, 2019
Resolve "Add Timestamp support to CAN Testlib"
!201
· created
Jan 15, 2019
by
Ing. Viktor Fúra
Test improvements
Merged
1
updated
Jan 20, 2019
Resolve "Align TIMESTAMP to 64 bit Address"
!195
· created
Jan 10, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 10, 2019
Resolve "Regmap gen saturation fix."
!192
· created
Jan 08, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 08, 2019
SRC REGISTERS Fixed reset.
!187
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
0
updated
Jan 06, 2019
TEST ALL Added Reg.map waves.
!186
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
Test improvements
Doing
Merged
0
updated
Jan 06, 2019
Added explicit warning to register descriptions. Some registers are
!185
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
4
updated
Jan 06, 2019
Resolve "SSP offset"
!183
· created
Jan 06, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 06, 2019
Swapped priority of set/reset for DOI interrupt. Added
!177
· created
Jan 02, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 02, 2019
Resolve "add registers for reading current timestamp"
!176
· created
Jan 02, 2019
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Jan 02, 2019
Resolve "Design decoupling"
!175
· created
Dec 30, 2018
by
Ille, Ondrej, Ing.
ISO optimizations
Merged
4
updated
Jan 02, 2019
Resolve "Extend pyxact generator with VHDL access generation"
!173
· created
Dec 09, 2018
by
Ille, Ondrej, Ing.
Wishlist
Merged
0
updated
Dec 09, 2018
Added Inferred RAM wrapper to TXT Buffers.
!169
· created
Oct 31, 2018
by
Ille, Ondrej, Ing.
ISO optimizations
Doing
Merged
0
updated
Oct 31, 2018
Resolve "Unify "others" clause!"
!129
· created
Jul 13, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
0
updated
Jul 13, 2018
Resolve "Bus off time"
!127
· created
Jul 12, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
0
updated
Jul 12, 2018
Resolve "TODO research"
!126
· created
Jul 10, 2018
by
Ille, Ondrej, Ing.
Bug fixing
Merged
0
updated
Jul 10, 2018
Prev
1
…
5
6
7
8
9
10
11
12
13
…
22
Next