Merge Requests · canbus / CTU CAN FD IP Core · GitLab

Added byte enable support

!18 · opened Dec 20, 2017 by Ille, Ondrej, Ing.
- MERGED
- 0
updated Dec 20, 2017
Automation of Core resource evaluation

!17 · opened Dec 20, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 20, 2017
Resource optimizations

!16 · opened Dec 19, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 19, 2017
Resource optimizations

!15 · opened Dec 15, 2017 by Ille, Ondrej, Ing. Design automation
- MERGED
- 0
updated Dec 15, 2017
Resource optimizations

!14 · opened Dec 13, 2017 by Ille, Ondrej, Ing. Bug fixing
- MERGED
- 0
updated Dec 13, 2017
Added bit-rate switch compensation of Ph2 segment

!13 · opened Dec 12, 2017 by Ille, Ondrej, Ing. Bug fixing
- MERGED
- 0
updated Dec 12, 2017
Renamed registers entity to "canfd_registers"

!12 · opened Dec 12, 2017 by Ille, Ondrej, Ing. Bug fixing
- MERGED
- 0
updated Dec 12, 2017
Changed license header of the project to MIT license

!11 · opened Dec 11, 2017 by Ille, Ondrej, Ing.
- MERGED
- 0
updated Dec 11, 2017
Resource optimizations

!10 · opened Dec 11, 2017 by Ille, Ondrej, Ing. Bug fixing
- MERGED
- 0
updated Dec 11, 2017
Resource optimizations

!9 · opened Dec 09, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 09, 2017
RX CRC reorganized

!8 · opened Dec 09, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 09, 2017
Resource optimizations

!7 · opened Dec 09, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 09, 2017
Added Readme to the repo

!6 · opened Dec 06, 2017 by Ille, Ondrej, Ing.
- MERGED
- 0
updated Dec 06, 2017
Resource optimizations

!5 · opened Dec 05, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 05, 2017
WIP: Resolve "TX buffer into SRAM"

!4 · opened Dec 05, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- CLOSED
- 0
updated Dec 05, 2017
Rx data to ram

!3 · opened Dec 01, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Dec 01, 2017
Rx data to ram

!2 · opened Nov 30, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- MERGED
- 0
updated Nov 30, 2017
WIP: Resolve "Serilize the receive data in the Protocol controller"

!1 · opened Nov 30, 2017 by Ille, Ondrej, Ing. FPGA resource optimization
- CLOSED
- 0
updated Nov 30, 2017

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