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CTU CAN FD IP Core
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  • CTU CAN FD IP Core
  • Issues

  • Open 14
  • Closed 387
  • All 401
New issue
  • Priority Created date Last updated Milestone due date Due date Popularity Label priority Manual
  • Github mirror
    #47 · opened Dec 27, 2017 by Ille, Ondrej, Ing.   To Do
    • CLOSED
    • 2
    updated Dec 11, 2018
  • Generate VHDL registers from IP-XACT
    #84 · opened Feb 08, 2018 by Ille, Ondrej, Ing.   ISO optimizations
    • CLOSED
    • 1
    updated Dec 09, 2018
  • Extend pyxact generator with VHDL access generation
    #109 · opened Apr 08, 2018 by Ille, Ondrej, Ing.   Wishlist
    • CLOSED
    • 2
    • 0
    updated Dec 09, 2018
  • Remove regmap gen files from project.
    #209 · opened Dec 08, 2018 by Ille, Ondrej, Ing.
    • CLOSED
    • 1
    • 0
    updated Dec 08, 2018
  • TX Buffer explicit memory
    #195 · opened Oct 29, 2018 by Ille, Ondrej, Ing.   ISO optimizations   Doing
    • CLOSED
    • 1
    • 0
    updated Oct 31, 2018
  • Avalon master interface
    #26 · opened Dec 06, 2017 by Ille, Ondrej, Ing.   DMA   Rejected
    • CLOSED
    • 1
    updated Oct 30, 2018
  • Fault confinement test
    #145 · opened May 29, 2018 by Ille, Ondrej, Ing.   ISO conformance testing   Rejected
    • CLOSED
    • 0
    updated Oct 29, 2018
  • Error and overload frame test
    #146 · opened May 29, 2018 by Ille, Ondrej, Ing.   ISO conformance testing   Rejected
    • CLOSED
    • 0
    updated Oct 29, 2018
  • Release 2.1 cleanup
    #193 · opened Oct 05, 2018 by Ille, Ondrej, Ing.   Release 2.1
    • CLOSED
    • 1
    • 0
    updated Oct 05, 2018
  • Documentation clarification
    #127 · opened May 01, 2018 by Ille, Ondrej, Ing.   Doing Release 2.1
    • CLOSED
    • 2
    • 8
    updated Oct 04, 2018
  • Update licence header
    #190 · opened Sep 24, 2018 by Ille, Ondrej, Ing.   Release 2.1
    • CLOSED
    • 1
    • 0
    updated Sep 28, 2018
  • Rename some register fields to "look familiar" or be more descriptive
    #135 · opened May 17, 2018 by Martin Jeřábek   Release 2.1
    • CLOSED
    • 1
    • 2
    updated Sep 28, 2018
  • RX Buffer RAM pipeline
    #181 · opened Aug 31, 2018 by Ille, Ondrej, Ing.   Release 2.1
    • CLOSED
    • 1
    • 2
    updated Sep 27, 2018
  • CI/CD: generate documentation and publish to Pages
    #143 · opened May 25, 2018 by Martin Jeřábek   Continuous integration   Release 2.1
    • CLOSED
    • 1
    • 8
    updated Sep 25, 2018
  • Message filter feature test
    #169 · opened Jul 10, 2018 by Ille, Ondrej, Ing.   Test maintenance   Doing Release 2.1
    • CLOSED
    • 1
    • 0
    updated Sep 21, 2018
  • Form error detection in delim_ack
    #174 · opened Jul 24, 2018 by Ille, Ondrej, Ing.   Release 2.1
    • CLOSED
    • 1
    • 0
    updated Sep 19, 2018
  • TXBHCI is triggered on wrong state transitions
    #176 · opened Jul 30, 2018 by Martin Jeřábek   Release 2.1
    • CLOSED
    • 3
    • 6
    updated Sep 18, 2018
  • Bus off time
    #128 · opened May 03, 2018 by Ille, Ondrej, Ing.   Bug fixing   Doing
    • CLOSED
    • 1
    • 0
    updated Sep 15, 2018
  • Unify "others" clause!
    #170 · opened Jul 10, 2018 by Ille, Ondrej, Ing.   Bug fixing   Doing
    • CLOSED
    • 1
    • 0
    updated Sep 15, 2018
  • Synthesis warning research
    #59 · opened Jan 18, 2018 by Ille, Ondrej, Ing.   Bug fixing   Doing
    • CLOSED
    • 1
    • 1
    updated Sep 15, 2018
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