Generate VHDL files documentation
Actual documentation in Chapter "System architecture" contains tables with inputs and outputs which are hard to maintain manually. These tables will be moved to appendix.
Extend the IP-XACT generator, or create a separate VHDL code documentator, which will fetch all VHDL source code files and generate these tables for us!
There are some obscure things however! Every file then must have equal format of description in the file header. Every signal in the port would need to have exact description format, which is little bit more problematic.