8 and 16 bit access extension
To have proper access one Avalon bus, byte enable signal must be added into the CAN Top level and registers module.
Actual implementation of the IP Core supports only full 32 bit accesses. The origin of the implementation is in the test platform where byte enable support was not needed. On the road to the full compatibility with the Avalon spec, byte enable signal must be added. Inactive bits of this signal will mask out the write data and not write the bytes which are forbidden for writing by byte-enable signal. Adding byte enable signal will add support for accessing the registers from uint8_t and uint16_t types in C. All side effects (like clearing interrupt vector by performing read) must be also masked out by byte enable signal.