Byte order of CAN farme data is wappped on big-endian system.
This problem can be solved in hardware or in the driver. Change in the driver is the right solution. Hardware swap for all word size registers would lead to inconsistency in the fields which are not byte wide. Change in only can frame related data in the Tx frame buffers is feasible and eliminates one bswap32 in the software. Change in Rx FIFO would require to store data byte swapped into FIFO because dynamically change read word endiannesss on the register read size according to read of metadata and actual data is problematic.
All these options are complicated and if there is no option to switch runtime order between byte data and wider registers dynamically then there is no feasible option to build PCI card which can work correctly in both, big-endian and little-endian systems.
Software side swap is relatively cheap on today CPU architectures. What is the best solution for DMA in future is questionable because SocketCAN does not define fixed byte order for identifier.