TX Arbitrator - extend arbitration
A bug was revealed in current TXT Buffer validation mechanism. When node starts transmitting frame as a result of sampling dominant in Bus idle or third bit of intermission, there will be not enough time for TXT Buffer RAM to provide Identifier word on its output, since at the same cycle Protocol control is issuing "Lock" and also preloading TX shift register with Base ID value. But at this time TX Arbitrator is still using its own pointer (it is not locked yet), therefore data provided to protocol control (as Base ID) are in reality Timestamp or Frame format words...
This bug was revealed on 28.9 during writing TC, for ALC register and it can manifestate itself in very different scenarios... (maybe this too: #313 (closed))
I have a solution for this:
- Extend TXT buffer validation process to load also Identifier word to capture register.
- TX shift register will load ID from capture register, not from TXT Buffer RAM.
Together, TX arbitrator FSM will have 3 new states:
Idle - No frame is "Selected", this is to replace default "Load lower timestamp" state. In this state, there will be no access to memory. This is a preparation for gating access to RAMs only when data truly needs to be read (#302)
Select ID - Loading ID to capture registers.
Validated - After TXT Buffer was validated, TX Arbitrator will stay here until selected TXT Buffer was changed or there is no buffer available anymore or Lock command arrives. This is also a preparation for solution of previously mentioned issue.
Note that drawback of this is: 29 more DFFs. But we dont care since: #261 (closed) will in the end save 128 - 16 = 112 DFFs!
- Describe the changes in System architecture (TX Arbitrator FSM diagram, use-cases).
- Implement changes in RTL.
- Verify that changes did fix the problem by cherry-picking feature test for ALC which is currently being written!