CAN FD TX Bit Error detection optimization
Statement of a problem:
CAN FD Transceiver in Data Bit-Rate must detect BIT Error. If value transmitted in Sync differs from value in Sample Point, Bit error should be detected.
Since Data Bit-Rate might be fast enough, secondary sampling mechanism is employed? What does it mean for Bit error detection in this case?
RX value sampled by delayed sampling point must be compared with TX Data value at the time of regular sampling point (or TX value that corresponds to the bit where original non-delayed sample point was).
Secondary sampling point is implemented via shift register where sampling point is piped into this register. Shift register output at index of ssp_offset is taken as delayed sampling point. This is OK to create delayed sampling point. Could be optimized somehow, but that is not the point now.
Another shift register is used to store value of TX Data. Shit register output at index of ssp_offset is taken and this gives us the original TX value at the time of regular sampling point.
What could be optimized is this second shift-register. We don't need to remember whole bit-stream per clock cycle. We only need to remember values sent in SYNC segments. Proposal is to create small cache/buffer FIFO-like where upon TX, new data will be appended to the end and upon active delayed sampled point last data will be read. In Shift-register only the last data are read anyway. If not, then we missed something and did not execute Bit Error comparison on a bit anyway...
Actually both shift registers have 130 entries. Removing one of them would lower the resource usage or maybe allow extending the other one...