ci: automatically generate FPGA bitstream
On master update, run a delayed nightly build of FPGA top-level design and make the bitstream available to speed up HW testing.
This issue really targets the toplevel repo https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top, but is included here as a means of (devel) "documentation".
Description is in AUTOBUILD.md. Bitstream may be downloaded from pipeline artifacts on branch autobuild_*.