Rewrite AXI wrapper to be fully synchronous
The current half-async AXI wrapper introduces path delay ~12ns, which is bad for high frequencies. For now we can test on 50MHz, but this needs to be rewritten to cut down on the delay, albeit for the price of one extra latency cycle.
If generated register access interface should happen to be implemented sooner than this, we may ditch this completely and use fully duplex AXI.