TX Arbitrator pipeline + Hazard unit
The latest (End of April 2018) synthesis results in Xilinx and Altera Technologies are limited by (not surprisingly) the same combinational paths. The maximum frequencies are somewhere around 90 - 95 MHz. It would be nice to move to 100 and above.
The reason for this is following:
- HW and SW commands are applied simultaneously and are completely asynchronous (not in the clock domain sense, rather in "both can happend at any time without knowing about each other").
- Due to 1. , SW Commands, HW commands and TXT Buffer priorities and "ready indication" are evaluated combinationally! Such an evaluation contains following combinational paths: A) Starts in SW command register and TXT Buffer priorities. B) Propagates through "priority decoder to "select_buf_index" and "select_buf_avail". C) These values are used to control flow of TX Arbitrator FSM (e.g. restarting on change of "select_buf_index"). D) TX Arbitrator FSM is loading metadata and timestamp from TXT Buffers. Since It takes one clock cycle for RAM, propagate data to the output, metadata_pointer in TX Arbitrator must be decoded combinationally! The same condition which causes TX Arbitrator FSM state transition, must be used to combinationally address word in TXT_Buffer memory in TXT Buffer word (address) which is needed by successive state of FSM. E) Due to combinational driver on "metadata_pointer", pointer to TXT RAM is not registered and causes path from A up to hard-core address decoder in RAM.
- Combinational paths from 2. cause problems in both Technologies (according to Martin Jerabek in Xilinx SoC, there is RAM problem), and in Altera Cyclone V, first 1000 worst paths (about first 2 ns slack) are caused by these paths.
To bring CTU CAN FD Core this problem must be resolved.
Following solutions are available:
- Implement pipeline between priority decoder and TX Arbitrator FSM. This would however require additional synchronisation of HW and SW command in new unit "e.g. Hazard unit to have cool naming..."
- Simpler solution would be to add new state to TX Arbitrator state machine, which would ALWAYS address metadata pointer with registered value! This would add next clock cycle to data loading (extend to 4 from 3 clock cycles), however it is easier solution than Hazard unit. One thing would still remain problematic. Address pointer would need to be set two clock cycles (two states) before data from its address are needed. This would be a problem in state where state transition is evaluated based on condition. Such a condition might have different value one clock cycle before, than during the cycle that causes the transition!