CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-02-04T22:15:44Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/1Serilize the receive data in the Protocol controller2021-02-04T22:15:44ZIlle, Ondrej, Ing.Serilize the receive data in the Protocol controllerThe rec_data signal in Protocol control is using "data_pointer" for addressing. Since the data are available on the output of
the core at all times. FFs are inferred for receive data.
This is not correct behaviour. Data should be record...The rec_data signal in Protocol control is using "data_pointer" for addressing. Since the data are available on the output of
the core at all times. FFs are inferred for receive data.
This is not correct behaviour. Data should be recorded by a shift register and stored into DP RAM. Since RX data are read serially
from Protocol controller (by RX buffer), this change does not matter.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/2TX Data optimizations2017-12-01T13:26:29ZIlle, Ondrej, Ing.TX Data optimizationsRemove first part of register pipeline for TX_DATA_X registers and replace it with direct access into the RAM memory.
This involves rewriting the TX buffer into array based memory.Remove first part of register pipeline for TX_DATA_X registers and replace it with direct access into the RAM memory.
This involves rewriting the TX buffer into array based memory.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/3Sync/Async reset2017-11-30T15:24:56ZIlle, Ondrej, Ing.Sync/Async resetAdd proper reset synchronisation.Add proper reset synchronisation.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/48 and 16 bit access extension2017-12-20T17:49:25ZIlle, Ondrej, Ing.8 and 16 bit access extensionTo have proper access one Avalon bus, byte enable signal must be added into
the CAN Top level and registers module.
Actual implementation of the IP Core supports only full 32 bit accesses. The origin of the implementation is in the test...To have proper access one Avalon bus, byte enable signal must be added into
the CAN Top level and registers module.
Actual implementation of the IP Core supports only full 32 bit accesses. The origin of the implementation is in the test platform where byte enable support was not needed. On the road to the full compatibility with the Avalon spec, byte enable signal must be added. Inactive bits of this signal will mask out the write data and not write the bytes which are forbidden for writing by byte-enable signal. Adding byte enable signal will add support for accessing the registers from uint8_t and uint16_t types in C. All side effects (like clearing interrupt vector by performing read) must be also masked out by byte enable signal.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/5Change of RX data read from RX buffer2017-12-19T16:28:55ZIlle, Ondrej, Ing.Change of RX data read from RX bufferThis modification involves changing architecture of the RX FIFO buffer. The RX FIFO buffer has actually parallel data interface from the IP Core (whole CAN frame is available in parallel). Once the frame is properly received (EOF field),...This modification involves changing architecture of the RX FIFO buffer. The RX FIFO buffer has actually parallel data interface from the IP Core (whole CAN frame is available in parallel). Once the frame is properly received (EOF field), the signal „rec_valid“ starts loading the frame into the RX buffer. The frame is stored in following up to 20 clock cycles, 32-bit word per clock cycle. The other part of the RX Buffer has only one 32-bit word at a time available. This word corresponds to address of the „read_pointer“ value. „read_pointer“ is incremented by each read on Avalon Interface. Read of the frame is performed by repetitive read from the same address.
The aim of this modification is to create the same interface between RX Buffer and registers (Avalon) as between RX Buffer and CAN Core. This involves modifying the register map of the IP Core. Offset on the Avalon bus will be added to the read pointer and it will create direct address to the RAM memory of RX Buffer. Avalon Adress must be added combinationally to the read pointer value, to be able to get the data on the output of the RAM in the next clock cycle. The multiplexor must be created to drive the RAM address based on the Avalon address range. Actual implementation moves to the next word in the memory (increments read pointer) by performing the Avalon read. Additional bit must be added to register map. Writing logic 1 into this bit will increment the value of the pointer to point to the first word of next CAN frame. Thus user would be responsible for erasing the frame from RX buffer after reading it!
An optional inference of the RX Buffer via VHDL generic must be added during this step. This option will allow to either inferr or not inferr the RX buffer. In the case of the buffer presence the Avalon address will create the RAM address based on chosen register. In the absence of the RX buffer the Avalon address would create the offset in the parallel interface on the ouput of CAN Core. In case of Buffer absence the user is responsible for reading the frame soon enough before the Core erases it at the SOF of next frame!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/6Retransmitt frame dropping2017-12-27T23:40:15ZIlle, Ondrej, Ing.Retransmitt frame droppingThe actual implementation rettransmitts the frame once the Core lost arbitration or error occured. The repetition of the re-transmission can be limited by the user. However if the retransmitt limit option is disabled the frame will re-tr...The actual implementation rettransmitts the frame once the Core lost arbitration or error occured. The repetition of the re-transmission can be limited by the user. However if the retransmitt limit option is disabled the frame will re-transmitt forever and might possibly block this core for longer time. The aim of this task is to detect if higher priority frame is present in either of TX Frames before re-transmitting the frame. If yes, the actual frame should be dropped, and the higher priority frame should be loaded to CAN Core for transmission. The behaviour must be configurable from user-registers. Thus user can choose whether the frame will be dropped or re-transmitted in presence of higher priority frame in the buffer. The implementation involves comparison between the actual frame identifier in the CAN Core and the Identifiers in the TX buffers. This feature will be implemented in the TX Arbitrator circuit or Protocol Control FSM.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/7TX buffer into SRAM2017-12-05T12:12:17ZIlle, Ondrej, Ing.TX buffer into SRAMThe actual implementation of the TXT buffer is using Flip-flops. In order to use SRAM memory on FPGA, the load of the data into the CAN core must be serialized, since FPGAs does not offer 640-bit width memories. This task involves creati...The actual implementation of the TXT buffer is using Flip-flops. In order to use SRAM memory on FPGA, the load of the data into the CAN core must be serialized, since FPGAs does not offer 640-bit width memories. This task involves creation of the FSM for serial loading the TX frame into CAN Core. This task must be implemented after the serialization of access from user registers and after adding the frame droppig feature and must be compliant with both of these features. As first, identifier must be loaded to the CAN Core, beacuse loading will také up to 20 clock cycles. If the identifier is not already stored in the CAN Core during the first bit of the Identifier transmission, Invalid value will be transmitted. This situation must be avoided.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/8Bug-fix of the switching between data rates2017-12-12T17:41:32ZIlle, Ondrej, Ing.Bug-fix of the switching between data ratesThe actual implementation of the Prescaler does compenasation for the bit time duration during bit-rate switching. This compensation depends always on the data bit time with the assumption that the nominal time quanta is set to value hig...The actual implementation of the Prescaler does compenasation for the bit time duration during bit-rate switching. This compensation depends always on the data bit time with the assumption that the nominal time quanta is set to value higher than 4. This behaviour is not correct and should be changed to support all combinations of Nominal Time quanta and Data Time Quanta duration. This behaviour was not observed in the reference hardware testing since value of 8 was used for nominal bit time prescaler and thus the bit counter truly was not affected.Bug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/9RX buffer unit test2018-06-08T12:40:52ZIlle, Ondrej, Ing.RX buffer unit testMake sure that RX buffer unit test run properly after changes in structure of reading the RX data.Make sure that RX buffer unit test run properly after changes in structure of reading the RX data.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/10TX buffer unit test2018-04-15T10:53:59ZIlle, Ondrej, Ing.TX buffer unit testRewrite the TX buffer unit test after change of TX Data handlingRewrite the TX buffer unit test after change of TX Data handlingTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/11Configurable filter support2017-12-05T12:12:36ZIlle, Ondrej, Ing.Configurable filter supportAdd configurable filter support. Thus it can be decided before synthesis if this filter will be supported.
Each filter needs identifier value and identifier mask 2*29 Flip-flops . Thus e.g. if only one identifier should be captured by a...Add configurable filter support. Thus it can be decided before synthesis if this filter will be supported.
Each filter needs identifier value and identifier mask 2*29 Flip-flops . Thus e.g. if only one identifier should be captured by any unit,
then it does not have sense to have support of all filters!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/12Rename the registers entity2017-12-12T15:03:38ZIlle, Ondrej, Ing.Rename the registers entityRename the registers entity to "cancore_registers" or sth like that.
Different modules might have different "registers" module thus the naming must be explicitRename the registers entity to "cancore_registers" or sth like that.
Different modules might have different "registers" module thus the naming must be explicitBug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/13Prescaler unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Prescaler unit testExtend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Extend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/14CAN CRC optimization2017-12-09T14:25:40ZIlle, Ondrej, Ing.CAN CRC optimizationAdd optimization for addressing of CAN CRC inside the Protocol control counter.
The idea is to load the CRC at the beginning of the CRC phase and use shift-register
during the transmission instead of direct adressing in the crc15,crc17,c...Add optimization for addressing of CAN CRC inside the Protocol control counter.
The idea is to load the CRC at the beginning of the CRC phase and use shift-register
during the transmission instead of direct adressing in the crc15,crc17,crc21 signals.
This should save some logic inside the protocol control!FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/15Bus sync optimization2018-01-02T23:00:16ZIlle, Ondrej, Ing.Bus sync optimizationssp_shift shift register for secondary sampling point of the Data phase during FD transmission is problematic from resource usage
point of view.
Think of solutions for this. Can we remove direct addressing?? I assume not, since the leng...ssp_shift shift register for secondary sampling point of the Data phase during FD transmission is problematic from resource usage
point of view.
Think of solutions for this. Can we remove direct addressing?? I assume not, since the length of the shift register
is not fixed (it is given by transceiver delay)...FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/16RX CRC optimization2017-12-09T14:27:58ZIlle, Ondrej, Ing.RX CRC optimizationRemove the direct addressing by shift-register on received CRC.Remove the direct addressing by shift-register on received CRC.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/17Identifier optimization2017-12-09T17:36:58ZIlle, Ondrej, Ing.Identifier optimizationUnify the identifier transmission in Protocol control.
Use shift register instead of direct addressing of the identifier.Unify the identifier transmission in Protocol control.
Use shift register instead of direct addressing of the identifier.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/18Register automatization2018-01-02T23:01:40ZIlle, Ondrej, Ing.Register automatizationCreate a python script which will generate the register structure from an uniform document.
Following structures must be generated:
1. VHDL include file with definition of addresses for each register, indices within register.
2. C heade...Create a python script which will generate the register structure from an uniform document.
Following structures must be generated:
1. VHDL include file with definition of addresses for each register, indices within register.
2. C header file which would contain the same for C driver!
3. Modify the Lyx documentation accordingly! (optional - most difficult)Design automationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/19Error code captur register2018-01-05T10:02:11ZIlle, Ondrej, Ing.Error code captur registerAdd Error code capture register as in SJA1000
according to where in the frame error ocurred.Add Error code capture register as in SJA1000
according to where in the frame error ocurred.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/20Create DMA address space2019-03-14T20:04:30ZIlle, Ondrej, Ing.Create DMA address spaceDesign DMA register map and describe it in the registers definitionDesign DMA register map and describe it in the registers definitionDMA