CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-02-20T08:14:07Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/405SETTINGS[TBFBO] feature test2021-02-20T08:14:07ZIlle, Ondrej, Ing.SETTINGS[TBFBO] feature testCurrently dedicated test is missing for TBFBO bit.Currently dedicated test is missing for TBFBO bit.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/404SSP at last bit - clarification2021-02-18T18:15:12ZIlle, Ondrej, Ing.SSP at last bit - clarificationIt should be clarified whether SSP which occurs just before SP
of CRC delimiter and detect bit error, shall also cause bit error!
ISO spec says that SSP shall be stopped at SP of CRC delimiter!
Therefore if SSP is configured so that it ...It should be clarified whether SSP which occurs just before SP
of CRC delimiter and detect bit error, shall also cause bit error!
ISO spec says that SSP shall be stopped at SP of CRC delimiter!
Therefore if SSP is configured so that it occurs just before SP
of CRC delimiter, it shall IMHO still detect bit error. This is
not the case at the moment. Bit error is detected, captured, but
ignored upon upcoming sample point in CTU CAN FD.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/403CAN Clock2021-06-19T15:53:23ZIlle, Ondrej, Ing.CAN ClockSplit CAN FD IP Core into two clock domains:
1. CAN Clock
2. System Clock
This is needed to meet oscillator tolerance requirements of CAN Bus. If this is not done, then
also Memory bus needs to be clocked from oscillator which meets bit...Split CAN FD IP Core into two clock domains:
1. CAN Clock
2. System Clock
This is needed to meet oscillator tolerance requirements of CAN Bus. If this is not done, then
also Memory bus needs to be clocked from oscillator which meets bit timing requirements on CAN bus!
Typical MCU usage would however require two clock domains!
1. [ ] Update System architecture with decision how it will be done (list all signals crossing CDC, and their CDC handling protocol). Decide about best/worst case clock frequencies ratio!
2. [ ] Update User-guide to take "CAN clock" into account.
3. [ ] Implement the change in RTL.
4. [ ] Debug existing tests.
5. [ ] Create tests / regressions which verify minimal/maximal ratios of clock frequencies.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/402License update2021-02-04T20:27:46ZIlle, Ondrej, Ing.License updatehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/401Add repository clean script2021-01-10T20:26:03ZIlle, Ondrej, Ing.Add repository clean scriptAdd REST API script to clean pipeline data.Add REST API script to clean pipeline data.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/400Datasheet and System Architecture clean-up2020-12-30T10:40:15ZIlle, Ondrej, Ing.Datasheet and System Architecture clean-uphttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/399Release package finalization2021-05-24T17:27:19ZIlle, Ondrej, Ing.Release package finalizationFrom artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component d...From artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component documentation.
4. [x] Result of latest regression, compliance regression, functional coverage.
5. [x] Xilinx and Altera FPGA components.
6. [x] Synthesis benchmark.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/398Memory testability on RTL2021-05-02T17:47:16ZIlle, Ondrej, Ing.Memory testability on RTLImplement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these ...Implement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these registers.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/397Scan mode support on RTL.2021-05-05T14:45:33ZIlle, Ondrej, Ing.Scan mode support on RTL.Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/396Use kernel compliant register map in linux driver2021-09-25T09:46:44ZIlle, Ondrej, Ing.Use kernel compliant register map in linux driverLinux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/395Generic number of TXT Buffers2021-02-24T01:34:17ZIlle, Ondrej, Ing.Generic number of TXT BuffersThis task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implemen...This task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implement the change in RTL.
4. [x] Extend feature tests to check all buffers (in feature TB config use 8 TXT Buffers).https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/394RX Buffer status extension2020-12-12T20:53:53ZIlle, Ondrej, Ing.RX Buffer status extensionImplement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] I...Implement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] Implement in RTL
3. [ ] Document
4. [ ] Write testISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/393Functional coverage fix2020-12-09T21:17:47ZIlle, Ondrej, Ing.Functional coverage fixTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/392Regression improvements2020-11-29T22:24:37ZIlle, Ondrej, Ing.Regression improvementsAdd test-cases to cover corner-cases of PSL coverage in TX Arbitrator.Add test-cases to cover corner-cases of PSL coverage in TX Arbitrator.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/391Fix hard synchronization upon SOF start2020-11-21T16:52:24ZIlle, Ondrej, Ing.Fix hard synchronization upon SOF startIf dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC ...If dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC FSM is already in s_pc_sof. This means that it reacts to resynchronisation.
This can be fixed that hard sync will be valid also during SOF, but this approach must
be analyzed first.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/390Extend reintegration2020-11-05T20:02:20ZIlle, Ondrej, Ing.Extend reintegrationReintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive...Reintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive bits earlier than the tester (remember its all recessive bits,
so no resynchronization) and retransmitt earlier.
Good approach how to avoid this, is to demand 129 consecutive recessive repetitions
of 11 consecutive recessive bits.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/389Datasheet clean-up vol. 22020-10-31T22:14:25ZIlle, Ondrej, Ing.Datasheet clean-up vol. 2Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to dis...Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to distuiguish betwen Base and Extended frames)
4. Add RTR suppression for frame filters.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/388No synchronisation for transmitter during data bit-rate2020-10-29T20:15:41ZIlle, Ondrej, Ing.No synchronisation for transmitter during data bit-rateCurrently, transmitter does not synchronize during data bit rate
only if there is SSP. If SSP is not used during data bit rate by
transmitter, it still re-synchronizes, which is wrong!Currently, transmitter does not synchronize during data bit rate
only if there is SSP. If SSP is not used during data bit rate by
transmitter, it still re-synchronizes, which is wrong!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/387AHB test2023-12-17T20:38:17ZIlle, Ondrej, Ing.AHB testAt the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)At the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/386driver: updates based on v6 patches review2020-10-26T11:34:23ZPavel Pisadriver: updates based on v6 patches reviewhttps://lkml.org/lkml/2020/10/22/249https://lkml.org/lkml/2020/10/22/249