CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2019-09-09T15:39:17Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/301Driver sources documentation.2019-09-09T15:39:17ZPavel PisaDriver sources documentation.Driver sources documentation should conform to kernel-doc style to make sources acceptable for mainline.
It is questionable if kernel-doc format is preferable for ctu_can_fd_hw.h but change is planned to to be consistent with ctu_can_fd.c.Driver sources documentation should conform to kernel-doc style to make sources acceptable for mainline.
It is questionable if kernel-doc format is preferable for ctu_can_fd_hw.h but change is planned to to be consistent with ctu_can_fd.c.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/302Extend TXT Buffer and RX Buffer RAMs2021-02-06T13:22:58ZIlle, Ondrej, Ing.Extend TXT Buffer and RX Buffer RAMsRight now, read is executed every clock cycle from these RAMs.
This is not desirable and "CE" or "RE" signal shall be added.
Thisway, RAM will load data only when CE is high and keep previous data on its output.
This needs to be added t...Right now, read is executed every clock cycle from these RAMs.
This is not desirable and "CE" or "RE" signal shall be added.
Thisway, RAM will load data only when CE is high and keep previous data on its output.
This needs to be added to TXT Buffer RAM and RX Buffer RAM. Inferred RAM wrapper must
be extended by these signals. CE signals shall be separate for each port.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/303Block BTR and BTR_FD during operation2019-12-06T16:41:31ZIlle, Ondrej, Ing.Block BTR and BTR_FD during operationCAN FD ISO standard says that bus timing parameters must be protected from being changed when CAN bus
communication is ongoing...
So far we can write to BTR and BTR_FD at any time. IP-xact generator can be extended by more "lock" signal...CAN FD ISO standard says that bus timing parameters must be protected from being changed when CAN bus
communication is ongoing...
So far we can write to BTR and BTR_FD at any time. IP-xact generator can be extended by more "lock" signals.
Right now single lock signal is used. Lock signal can be specified as value in Vendor Extensions of IP-XACT.
This-way write to BTR and BTR_FD will be gated by value of SETTTINGS[ENA]ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/304TX arbitrator optimization2019-10-05T07:03:31ZIlle, Ondrej, Ing.TX arbitrator optimizationTX arbitrator now loads data from TXT buffer in circular manner during TXT buffer validation process.
By this I mean that timestamp words are read, timestamp comparison is executed, frame format word is read
and loaded to capture regist...TX arbitrator now loads data from TXT buffer in circular manner during TXT buffer validation process.
By this I mean that timestamp words are read, timestamp comparison is executed, frame format word is read
and loaded to capture registers. Then, the same procedure repeats even if this does not have sense because
the same data will be selected. The procedure shall be restarted only when Selected TXT Buffer changes because
then new frame can be loaded. Power-wise reading from such a big RAM data again and again redundantly is not
very good approach (even for FPGAs)https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/305Set Abort + Retransmitt counter2019-10-05T10:25:45ZIlle, Ondrej, Ing.Set Abort + Retransmitt counterWhen TXT Buffer FSM moves to Aborted, and this buffer was used for last transmission, Retransmitt counter should
be cleared. This TODO is further explained in TX arbitrator section.When TXT Buffer FSM moves to Aborted, and this buffer was used for last transmission, Retransmitt counter should
be cleared. This TODO is further explained in TX arbitrator section.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/306Synchronization edge by Time Quanta2019-12-02T19:30:08ZIlle, Ondrej, Ing.Synchronization edge by Time QuantaAdd gating which will detect synchronization edges only when Time Quanta is active!
Right now synchronisation edge is detected with System clock period, captured and processed
when Time Quanta Edge is active. This exposes potential vuler...Add gating which will detect synchronization edges only when Time Quanta is active!
Right now synchronisation edge is detected with System clock period, captured and processed
when Time Quanta Edge is active. This exposes potential vulerability when short sub-time-quanta
glitches will be applied that these will in the end cause resynchronisation!!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/307Resolve reset synchronisation in APB/AHB wrappers2021-05-16T18:22:10ZIlle, Ondrej, Ing.Resolve reset synchronisation in APB/AHB wrappersReset is defined as Asynchronous for CTU CAN FD but it is taken as reset in APB and AHB wrappers directly.
Reset synchronizer is only inside on CAN_top_level!
For AHB, protocol spec declares that reset is already synchronized (should be...Reset is defined as Asynchronous for CTU CAN FD but it is taken as reset in APB and AHB wrappers directly.
Reset synchronizer is only inside on CAN_top_level!
For AHB, protocol spec declares that reset is already synchronized (should be released synchronously), for
APB, it does not say anything. I think best approach would be to bring out synchronized reset on CAN_top_level
and use it to reset registers in APB/AHB wrapper! THis-way we dont add next reset synchronizers but still
resynchronize the reset by ourselves! Datasheet already defines that reset is asynchronous and is internally
synchronize and that other systems should not access it 2 clock cycles after it is released.
What do you think @pisa ??https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/308Remove tripple sampling mode from driver2019-10-30T21:58:47ZIlle, Ondrej, Ing.Remove tripple sampling mode from driverThis is a legacy feature and shall be removed as it is not present in HW anymore!This is a legacy feature and shall be removed as it is not present in HW anymore!Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/309RX traffic counter test2019-09-28T09:19:24ZIlle, Ondrej, Ing.RX traffic counter testAdd feature test for RX traffic counter.
This one should cover stuff like:
1. RX counter is incremented when frame is received at EOF.
(No need to verify exact position within EOF, this should be done in ISO conformance tests)
2. RX co...Add feature test for RX traffic counter.
This one should cover stuff like:
1. RX counter is incremented when frame is received at EOF.
(No need to verify exact position within EOF, this should be done in ISO conformance tests)
2. RX counter is not incremented when received frame is corrupted by error frame.
3. RX counter is not incremented when frame is transmitted.
4. RX counter is not cleared by COMMAND[TXFRCRST].
5. RX counter is cleared by COMMAND[RXFRCRST].Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/310Add system architecture to pages2019-09-26T21:52:45ZIlle, Ondrej, Ing.Add system architecture to pageshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/311Feature test clean-up2019-11-08T03:03:21ZIlle, Ondrej, Ing.Feature test clean-upRemove obsolete feature tests, modify existing ones to reflect newest expected HW behvaiour.Remove obsolete feature tests, modify existing ones to reflect newest expected HW behvaiour.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/312Communication errors uccur sometimes when sending message2019-11-29T14:24:18ZJaroslav BeranCommunication errors uccur sometimes when sending messageI've been testing a simple communication on 2-node bus with a PC with Kvaser Memorator Pro 2xHs v2 as the first node and Altera Cyclone V SoC with CTU_CAN_FD IP instantiated in FPGA as the second.
**Setup on both nodes:**
```
# ip link ...I've been testing a simple communication on 2-node bus with a PC with Kvaser Memorator Pro 2xHs v2 as the first node and Altera Cyclone V SoC with CTU_CAN_FD IP instantiated in FPGA as the second.
**Setup on both nodes:**
```
# ip link set can0 up type can \
bitrate 1000000 \
dbitrate 1000000 \
fd on
```
The problem occurs sometimes (it's relatively easy to achieve) when CTUCANFD node tries to send a message on the bus. I get errors from driver in kernel log and communication is stuck.
Sometimes it doesn't trigger on the first try, so play with messages like this:
```
[CTUCANFD NODE] # cansend can0 012#00.cc.ee
```
And it's correctly received on the other node:
```
[KVASER NODE] # candump can1
can1 012 [3] 00 CC EE
```
Then after some time for some unknown reason when I try to send another message (it can be FD or normal), I get errors from the driver.
```
[CTUCANFD NODE] # cansend can0 012##100.cc.ee
```
However cansend returns 0 and no message is received by other node on the bus.
**Kernel log on CTUCANFD NODE:**
```
[ 338.750082] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 96, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.763340] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.769160] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000014, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.782487] ctucanfd c0041000.ctu_can_fd can0: Fault conf: state = 3
[ 338.788985] ctucanfd c0041000.ctu_can_fd can0: bus_off
[ 338.795853] ctucanfd c0041000.ctu_can_fd can0: bus-off
[ 338.800995] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.814323] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.820136] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.833460] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.839272] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.852596] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.858408] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.871732] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.877545] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.890870] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.896683] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.910007] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.915817] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.929142] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.934953] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000004, rxerr 256, txerr 0, error type 0, pos 2, ALC id_field 0, bit 0
[ 338.948277] ctucanfd c0041000.ctu_can_fd can0: error_warning
[ 338.976765] ctucanfd c0041000.ctu_can_fd can0: ctucan_interrupt: stuck interrupt (isr=0x00000004), stopping
```
**Interface stats:**
```
[CTUCANFD NODE] # ip -d -s link show can0
4: can0: <NO-CARRIER,NOARP,UP,ECHO> mtu 72 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 10
link/can promiscuity 0 minmtu 0 maxmtu 0
can <FD> state ERROR-WARNING (berr-counter tx 0 rx 256) restart-ms 0
bitrate 1000000 sample-point 0.740
tq 20 prop-seg 18 phase-seg1 18 phase-seg2 13 sjw 1
ctu_can_fd: tseg1 2..190 tseg2 1..63 sjw 1..31 brp 1..8 brp-inc 1
dbitrate 1000000 dsample-point 0.740
dtq 20 dprop-seg 18 dphase-seg1 18 dphase-seg2 13 dsjw 1
ctu_can_fd: dtseg1 2..94 dtseg2 1..31 dsjw 1..31 dbrp 1..2 dbrp-inc 1
clock 50000000
re-started bus-errors arbit-lost error-warn error-pass bus-off
0 0 0 10000 0 1 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
RX: bytes packets errors dropped overrun mcast
80028 10007 0 9000 0 0
TX: bytes packets errors dropped carrier collsns
24 7 0 0 0 0
```
On Kvaser node, there are some errors detected as well:
```
[KVASER NODE] # ip -d -s link show can1
13: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP group default qlen 10
link/can promiscuity 0 minmtu 0 maxmtu 0
can <FD> state ERROR-ACTIVE (berr-counter tx 0 rx 32) restart-ms 0
bitrate 1000000 sample-point 0.750
tq 12 prop-seg 29 phase-seg1 30 phase-seg2 20 sjw 1
kvaser_usb_kcan: tseg1 1..255 tseg2 1..32 sjw 1..16 brp 1..4096 brp-inc 1
dbitrate 1000000 dsample-point 0.750
dtq 12 dprop-seg 29 dphase-seg1 30 dphase-seg2 20 dsjw 1
kvaser_usb_kcan: dtseg1 1..255 dtseg2 1..32 dsjw 1..16 dbrp 1..4096 dbrp-inc 1
clock 80000000
re-started bus-errors arbit-lost error-warn error-pass bus-off
0 117 0 1 1 1 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
RX: bytes packets errors dropped overrun mcast
959 126 117 0 0 0
TX: bytes packets errors dropped carrier collsns
4 4 0 2 0 0
```
From now communication is stuck unless I manually disable and enable the failing interface on CTUCANFD node, but even after that, every further message sent from CTUCANFD node triggers this error (even if I reset all interfaces, not just the failing).https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/313Errors on ID and/or data collision2019-11-29T14:24:37ZJaroslav BeranErrors on ID and/or data collision### System setup
Altera SoC Cyclone V, two CTU_CAN_FD controllers connected over a cable.
### Interafaces setup
```
# ip link set can0 up type can \
bitrate 1000000 \
dbitrate 1000000 \
fd on
[ 57.499341] ctuc...### System setup
Altera SoC Cyclone V, two CTU_CAN_FD controllers connected over a cable.
### Interafaces setup
```
# ip link set can0 up type can \
bitrate 1000000 \
dbitrate 1000000 \
fd on
[ 57.499341] ctucanfd c0041000.ctu_can_fd can0: ctu_can_fd device registered
[ 57.506293] ctucanfd c0041000.ctu_can_fd can0: ctucan_err_interrupt: ISR = 0x00000010, rxerr 0, txerr 0, error type 0, pos 31, ALC id_field 0, bit 0
[ 57.506304] ctucanfd c0041000.ctu_can_fd can0: Fault conf: state = 0
[ 57.506310] ctucanfd c0041000.ctu_can_fd can0: reached error active state
[ 57.533324] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
# ip link set can1 up type can \
bitrate 1000000 \
dbitrate 1000000 \
fd on
```
### Induce of the error state
1. Start generating some messages:
```
# while cansend can0 011#bb.cc.ee;do true; done
```
2. And then on the other interface start generating messages with the same ID
```
# while cansend can1 011#11.22.33;do true; done
```
The behavior slightly differs depending on whether the data field of both messages differs or is the same:
- When data field of both messages differs both `cansend` will fail with error `write: No buffer space available` (which is expected).
- When data fields are the same (so the entire message is the same) one `cansend` fails with `write: No buffer space available` but the other keeps running with no data being sent on the bus
**Kernel log:**
```
[ 253.197806] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 96, txerr 0, error type 0, pos 3, ALC id_field 0, bit 0
[ 253.211074] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.216942] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000c14, rxerr 124, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.230295] ctucanfd c0052000.ctu_can_fd can1: Fault conf: state = 1
[ 253.236814] ctucanfd c0052000.ctu_can_fd can1: error_warning, but ISR[FCSI] was set! (HW bug?)
[ 253.245757] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.251605] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000804, rxerr 120, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.264953] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.270812] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000804, rxerr 116, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.284161] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.290007] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000804, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.303339] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.309155] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.322482] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.328294] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.341619] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.347431] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.360756] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.366567] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.379892] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.385704] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 112, txerr 0, error type 2, pos 7, ALC id_field 0, bit 0
[ 253.399028] ctucanfd c0052000.ctu_can_fd can1: error_warning
[ 253.424568] ctucanfd c0052000.ctu_can_fd can1: ctucan_interrupt: stuck interrupt (isr=0x00000004), stopping
[ 253.434351] ------------[ cut here ]------------
[ 253.438968] WARNING: CPU: 0 PID: 24969 at net/core/skbuff.c:617 skb_release_head_state+0x9c/0xa4
[ 253.447712] Modules linked in: ctucanfd(O)
[ 253.451802] CPU: 0 PID: 24969 Comm: bash Tainted: G O 5.1.0+ #1
[ 253.458991] Hardware name: Altera SOCFPGA
[ 253.462980] Backtrace:
[ 253.465427] [<c010e554>] (dump_backtrace) from [<c010e7dc>] (show_stack+0x20/0x24)
[ 253.472964] r7:00000269 r6:60010193 r5:00000000 r4:c0c7a978
[ 253.478606] [<c010e7bc>] (show_stack) from [<c080f4d0>] (dump_stack+0x90/0xa4)
[ 253.485803] [<c080f440>] (dump_stack) from [<c0123134>] (__warn.part.3+0xcc/0xe8)
[ 253.493253] r7:00000269 r6:00000009 r5:00000000 r4:00000000
[ 253.498892] [<c0123068>] (__warn.part.3) from [<c01232d0>] (warn_slowpath_null+0x54/0x5c)
[ 253.507032] r7:c0b8bc80 r6:c069ff64 r5:00000269 r4:c0a4602c
[ 253.512671] [<c012327c>] (warn_slowpath_null) from [<c069ff64>] (skb_release_head_state+0x9c/0xa4)
[ 253.521590] r6:edc3d540 r5:c06b0e40 r4:edc3d540
[ 253.526190] [<c069fec8>] (skb_release_head_state) from [<c069ff88>] (skb_release_all+0x1c/0x34)
[ 253.534847] r5:c06b0e40 r4:edc3d540
[ 253.538409] [<c069ff6c>] (skb_release_all) from [<c06a0014>] (kfree_skb+0x4c/0xd8)
[ 253.545942] r5:c06b0e40 r4:edc3d540
[ 253.549508] [<c069ffc8>] (kfree_skb) from [<c06b0e40>] (enqueue_to_backlog+0xc0/0x22c)
[ 253.557388] r7:c0b8bc80 r6:edc3d540 r5:c0b8bc80 r4:ef7cfc80
[ 253.563027] [<c06b0d80>] (enqueue_to_backlog) from [<c06b84bc>] (netif_rx_internal+0x90/0x1b0)
[ 253.571602] r10:ededf000 r9:00000002 r8:00000000 r7:00000001 r6:edc3d540 r5:c0ca5a28
[ 253.579395] r4:c0c08c48 r3:edff6000
[ 253.582959] [<c06b842c>] (netif_rx_internal) from [<c06b8640>] (netif_rx+0x34/0x124)
[ 253.590668] r7:00000001 r6:ededf604 r5:ededf5e8 r4:edc3d540
[ 253.596311] [<c06b860c>] (netif_rx) from [<c05b8abc>] (can_get_echo_skb+0x40/0x60)
[ 253.603844] r5:ededf5e8 r4:c0c08c48
[ 253.607416] [<c05b8a7c>] (can_get_echo_skb) from [<bf000844>] (ctucan_interrupt+0x314/0x75c [ctucanfd])
[ 253.616764] r4:00000002
[ 253.619295] [<bf000530>] (ctucan_interrupt [ctucanfd]) from [<c0172b8c>] (__handle_irq_event_percpu+0xa8/0x278)
[ 253.629339] r10:c0c805e0 r9:edff7a68 r8:ef080800 r7:0000002b r6:00000000 r5:ef1b4d68
[ 253.637131] r4:ee8ac740
[ 253.639657] [<c0172ae4>] (__handle_irq_event_percpu) from [<c0172d98>] (handle_irq_event_percpu+0x3c/0x90)
[ 253.649267] r10:ffffe000 r9:f0803100 r8:ef080800 r7:00000001 r6:ef1b4d00 r5:ef1b4d68
[ 253.657059] r4:c0c08c48
[ 253.659584] [<c0172d5c>] (handle_irq_event_percpu) from [<c0172e40>] (handle_irq_event+0x54/0x78)
[ 253.668415] r6:edff7c40 r5:ef1b4d68 r4:ef1b4d00
[ 253.673017] [<c0172dec>] (handle_irq_event) from [<c0177678>] (handle_fasteoi_irq+0xc4/0x17c)
[ 253.681503] r7:00000001 r6:edff7c40 r5:c0c093d0 r4:ef1b4d00
[ 253.687145] [<c01775b4>] (handle_fasteoi_irq) from [<c0171ba4>] (generic_handle_irq+0x34/0x44)
[ 253.695715] r5:00000000 r4:c0b8af38
[ 253.699278] [<c0171b70>] (generic_handle_irq) from [<c0172298>] (__handle_domain_irq+0x6c/0xc4)
[ 253.707940] [<c017222c>] (__handle_domain_irq) from [<c01022e8>] (gic_handle_irq+0x5c/0xa0)
[ 253.716256] r9:f0803100 r8:edff7b28 r7:f0802100 r6:f080210c r5:c0c528e8 r4:c0c093d0
[ 253.723966] [<c010228c>] (gic_handle_irq) from [<c0101a8c>] (__irq_svc+0x6c/0x90)
[ 253.731414] Exception stack(0xedff7b28 to 0xedff7b70)
[ 253.736437] 7b20: c0b8af80 00000000 2ec44000 c0b8af80 00404040 00000000
[ 253.744580] 7b40: 00000000 00000001 ef080800 0000000c ffffe000 edff7bdc 2ec44000 edff7b78
[ 253.752719] 7b60: 00404040 c01023ec 60010113 ffffffff
[ 253.757751] r9:edff6000 r8:ef080800 r7:edff7b5c r6:ffffffff r5:60010113 r4:c01023ec
[ 253.765463] [<c0102330>] (__do_softirq) from [<c0129898>] (irq_exit+0x88/0x94)
[ 253.772655] r10:b6e6d000 r9:f0803100 r8:ef080800 r7:00000001 r6:00000000 r5:00000000
[ 253.780447] r4:c0b8af38
[ 253.782972] [<c0129810>] (irq_exit) from [<c017229c>] (__handle_domain_irq+0x70/0xc4)
[ 253.790767] [<c017222c>] (__handle_domain_irq) from [<c01022e8>] (gic_handle_irq+0x5c/0xa0)
[ 253.799081] r9:f0803100 r8:edff7c40 r7:f0802100 r6:f080210c r5:c0c528e8 r4:c0c093d0
[ 253.806790] [<c010228c>] (gic_handle_irq) from [<c0101a8c>] (__irq_svc+0x6c/0x90)
[ 253.814236] Exception stack(0xedff7c40 to 0xedff7c88)
[ 253.819268] 7c40: ee6810c0 b6e6d000 3f70959f 00000001 3f70959f ffefe1b8 b6e6d000 effe7100
[ 253.827410] 7c60: ffefe1b4 edff7da4 b6e6d000 edff7ca4 edff7ca8 edff7c90 c024be7c c024b544
[ 253.835548] 7c80: 20010013 ffffffff
[ 253.839024] r9:edff6000 r8:ffefe1b4 r7:edff7c74 r6:ffffffff r5:20010013 r4:c024b544
[ 253.846737] [<c024b538>] (_vm_normal_page) from [<c024be7c>] (unmap_page_range+0x224/0x718)
[ 253.855048] r5:ffefe1b8 r4:3f70959f
[ 253.858610] [<c024bc58>] (unmap_page_range) from [<c024c3fc>] (unmap_single_vma+0x8c/0x94)
[ 253.866838] r10:edff7e60 r9:00000001 r8:00000000 r7:edff7da4 r6:b6d96000 r5:ee6810c0
[ 253.874631] r4:b6eca000
[ 253.877155] [<c024c370>] (unmap_single_vma) from [<c024c56c>] (unmap_vmas+0x64/0x78)
[ 253.884863] r7:00000000 r6:edff7da4 r5:ffffffff r4:ee6810c0
[ 253.890500] [<c024c508>] (unmap_vmas) from [<c0252e48>] (exit_mmap+0xe0/0x17c)
[ 253.897691] r8:ef3cec00 r7:ef3cec00 r6:c0c08c48 r5:00000000 r4:ee6816c0
[ 253.904365] [<c0252d68>] (exit_mmap) from [<c011fee0>] (mmput+0x58/0x100)
[ 253.911124] r7:ee6cbc00 r6:ef3cf800 r5:00000000 r4:ef3cec00
[ 253.916764] [<c011fe88>] (mmput) from [<c027d734>] (flush_old_exec+0x4ec/0x704)
[ 253.924039] r5:ef3cec00 r4:eea5ce00
[ 253.927606] [<c027d248>] (flush_old_exec) from [<c02d9124>] (load_elf_binary+0x21c/0x14f4)
[ 253.935835] r10:edff7e60 r9:00000001 r8:ee6cb400 r7:edea45b4 r6:ee6cbc00 r5:c0c08c48
[ 253.943627] r4:edea4580
[ 253.946154] [<c02d8f08>] (load_elf_binary) from [<c027d9f8>] (search_binary_handler.part.2+0xac/0x24c)
[ 253.955420] r10:ee6cbc00 r9:c09f43e8 r8:c0c9ce60 r7:c0c25644 r6:fffffff8 r5:c0c9ce60
[ 253.963211] r4:c0c28500
[ 253.965738] [<c027d94c>] (search_binary_handler.part.2) from [<c027e1e4>] (__do_execve_file+0x57c/0x83c)
[ 253.975176] r10:ee6cbc00 r9:00006189 r8:00006189 r7:ffffe000 r6:eea5ce00 r5:ee4f9000
[ 253.982968] r4:c0c08c48
[ 253.985494] [<c027dc68>] (__do_execve_file) from [<c027e9b8>] (sys_execve+0x44/0x4c)
[ 253.993204] r10:0000000b r9:edff6000 r8:c0101204 r7:0000000b r6:00514728 r5:005163c8
[ 254.000997] r4:00503808
[ 254.003523] [<c027e974>] (sys_execve) from [<c0101000>] (ret_fast_syscall+0x0/0x54)
[ 254.011142] Exception stack(0xedff7fa8 to 0xedff7ff0)
[ 254.016171] 7fa0: 004f34bc 004f34bc 00514728 00503808 005163c8 f0de3100
[ 254.024314] 7fc0: 004f34bc 004f34bc 00514728 0000000b 004f84dc 00503808 005163c8 b6f848c8
[ 254.032452] 7fe0: 004f3790 be8f3734 004513f0 b6e3795c
[ 254.037481] r5:004f34bc r4:004f34bc
[ 254.041039] ---[ end trace d3e1f1104b9555ca ]---
[ 254.045663] ctucanfd c0041000.ctu_can_fd can0: Fault conf: state = 2
[ 254.052163] ctucanfd c0041000.ctu_can_fd can0: error_passive
[ 254.078239] ctucanfd c0041000.ctu_can_fd can0: ctucan_interrupt: stuck interrupt (isr=0x00000004), stopping
[ 254.088247] ctucanfd c0041000.ctu_can_fd can0: rx fifo overflow
```https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/314Component for Quartus / Platform Designer (Qsys)2019-10-28T17:01:54ZJaroslav BeranComponent for Quartus / Platform Designer (Qsys)Add an Tcl script for generating ctu_can_fd component for Intel Platform DesignerAdd an Tcl script for generating ctu_can_fd component for Intel Platform Designerhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/315TX Arbitrator - extend arbitration2019-10-02T19:57:50ZIlle, Ondrej, Ing.TX Arbitrator - extend arbitrationA bug was revealed in current TXT Buffer validation mechanism. When node starts
transmitting frame as a result of sampling dominant in Bus idle or third bit of intermission,
there will be not enough time for TXT Buffer RAM to provide Ide...A bug was revealed in current TXT Buffer validation mechanism. When node starts
transmitting frame as a result of sampling dominant in Bus idle or third bit of intermission,
there will be not enough time for TXT Buffer RAM to provide Identifier word on its output,
since at the same cycle Protocol control is issuing "Lock" and also preloading TX shift
register with Base ID value. But at this time TX Arbitrator is still using its own pointer
(it is not locked yet), therefore data provided to protocol control (as Base ID) are in
reality Timestamp or Frame format words...
This bug was revealed on 28.9 during writing TC, for ALC register and it can manifestate
itself in very different scenarios...
(maybe this too: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/issues/313)
I have a solution for this:
1. Extend TXT buffer validation process to load also Identifier word to capture register.
2. TX shift register will load ID from capture register, not from TXT Buffer RAM.
Together, TX arbitrator FSM will have 3 new states:
**Idle** - No frame is "Selected", this is to replace default "Load lower timestamp" state.
In this state, there will be no access to memory. This is a preparation for
gating access to RAMs only when data truly needs to be read (https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/issues/302)
**Select ID** - Loading ID to capture registers.
**Validated** - After TXT Buffer was validated, TX Arbitrator will stay here until selected
TXT Buffer was changed or there is no buffer available anymore or Lock command arrives.
This is also a preparation for solution of previously mentioned issue.
Note that drawback of this is: 29 more DFFs. But we dont care since: https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/issues/261
will in the end save 128 - 16 = 112 DFFs!
1. [ ] Describe the changes in System architecture (TX Arbitrator FSM diagram, use-cases).
2. [ ] Implement changes in RTL.
3. [ ] Verify that changes did fix the problem by cherry-picking feature test for ALC which is
currently being written!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/316Stuff counter when SOF is not transmitted2019-10-07T18:40:07ZIlle, Ondrej, Ing.Stuff counter when SOF is not transmittedWhen CTU CAN FD joins transmission as a result of sampling Dominant bit in third bit of Intermission
or during Bus idle, it does not transmitt SOF, this is fine and according to standard.
But it does not account this (received) SOF in C...When CTU CAN FD joins transmission as a result of sampling Dominant bit in third bit of Intermission
or during Bus idle, it does not transmitt SOF, this is fine and according to standard.
But it does not account this (received) SOF in Counter of equal consecutive bits in Bit Stuffing module.
Therefore if CAN frame with first 5 bits of ID dominant is transmitted, transmitter which joined the
communication (without SOF), inserts Stuff bit after 5 bits of ID. Other transmitter which did transmitt
SOF, will insert Stuff bit after 4 bits of ID and therefore detect Stuff Error on 5th bit of ID.
This behaviour is OK according to standard and there is an exception that Stuff bit during arbitration
shall not increment error counters. Question is, should we implement some workaround on top of existing
standard @pisa ? @beranj25 ? @jnovak ?ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/317Add driver doc to gitlab2019-10-06T17:12:25ZIlle, Ondrej, Ing.Add driver doc to gitlabhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/318Remove CAN ID from can_top_level.2019-10-09T19:42:19ZIlle, Ondrej, Ing.Remove CAN ID from can_top_level.Remove CAN ID generic from CAN_top_level.vhdRemove CAN ID generic from CAN_top_level.vhdISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/319Fix flipped TXC, RXC in driver.2019-10-09T19:18:11ZIlle, Ondrej, Ing.Fix flipped TXC, RXC in driver.Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/320Edge based EWL Interrupt2019-10-16T21:01:38ZIlle, Ondrej, Ing.Edge based EWL InterruptImplement EWL Interrupt to be edge based, not level-based.Implement EWL Interrupt to be edge based, not level-based.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/321Fix active error overload flag signalling2019-10-09T19:57:52ZIlle, Ondrej, Ing.Fix active error overload flag signallingSignalling of active error flag, overload flag shall not be active in Passive Error flag!Signalling of active error flag, overload flag shall not be active in Passive Error flag!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/322Linux driver review2019-10-30T21:51:43ZIlle, Ondrej, Ing.Linux driver reviewLinux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/323Add Protocol control exception on r0 after FDF2020-05-02T11:24:05ZIlle, Ondrej, Ing.Add Protocol control exception on r0 after FDFAdd protocol control exception in CAN FD frames to allow further extensions to of CAN frame
protocol. Behaviour shall be configurable by a userspace bit.Add protocol control exception in CAN FD frames to allow further extensions to of CAN frame
protocol. Behaviour shall be configurable by a userspace bit.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/324Do not return TX_OK2019-10-23T18:24:54ZIlle, Ondrej, Ing.Do not return TX_OKModify Linux driver not to return NETDEV_TX_OK when failed to insert CAN frame!Modify Linux driver not to return NETDEV_TX_OK when failed to insert CAN frame!Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/325ctucan top level compoenets names.2020-10-28T16:34:26ZPavel Pisactucan top level compoenets names.can_top_ahb, can_top_apb and can_top_level files and components should be renamed probably.
It is incorrect to claim can_ prefix name for components by CTU CAN FD project.
I suggest to change toplevel to ctucan_top_level etc.
If there...can_top_ahb, can_top_apb and can_top_level files and components should be renamed probably.
It is incorrect to claim can_ prefix name for components by CTU CAN FD project.
I suggest to change toplevel to ctucan_top_level etc.
If there is clean option how to keep different name for packaged IP core and implementing VHDL design component then it is not critical. In the fact, I would prefer to use even ctucanfd_ prefix, because IP core is limited to FD functionality in current form and for CAN XL different layout of TX buffers would be required. On the other hand, if ctucan_ is forked and then FD and XL branches are updated sometimes independently, sometimes by cherry picking or in sync then the common toplevel component name can help. So the preference between ctucanfd_ and ctucan_ is questionable. But use of ctucan_ instead of can_ is critical to update Vivado component which uses CTU_CAN_FD_v1_0 matching past integration mechanisms.
I am not sure if the version should be included or not. Vivado prefers version. It makes sense to integrate and compare behavior of two versions of the same core in single testbed/design. But from the GIT source versioning renaming the file is bad. For component name it makes problems to users but on the other had alarms user when fundamental change happens. So this is questionable.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/326Missing TX spinlock release leads to deadlock2019-10-28T16:08:15ZJaroslav BeranMissing TX spinlock release leads to deadlockIn case the _TXB not in a finished state_ bug uccurs, TX spinlock isn't unlocked before returning from `ctucan_tx_interrupt`, which results in deadlock.In case the _TXB not in a finished state_ bug uccurs, TX spinlock isn't unlocked before returning from `ctucan_tx_interrupt`, which results in deadlock.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/327Fix forgotten line removal2019-10-25T17:49:53ZIlle, Ondrej, Ing.Fix forgotten line removalhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/328FCSI, EWLI trigger and handling2019-11-07T01:12:42ZJaroslav BeranFCSI, EWLI trigger and handlingThe interrupt triggering improved much in last revisions, still there are some issues.
##### HW
```
[ 140.658852] ctucanfd c0052000.ctu_can_fd can1: ctu_can_fd device registered
[ 140.658872] ctucanfd c0052000.ctu_can_fd can1: ctucan...The interrupt triggering improved much in last revisions, still there are some issues.
##### HW
```
[ 140.658852] ctucanfd c0052000.ctu_can_fd can1: ctu_can_fd device registered
[ 140.658872] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000010, rxerr 0, txerr 0, error type 0, pos 31, ALC id_field 0, bit 0
[ 140.679047] ctucanfd c0052000.ctu_can_fd can1: Fault conf: state = 0
[ 140.685546] ctucanfd c0052000.ctu_can_fd can1: reached error active state
[ 140.692811] IPv6: ADDRCONF(NETDEV_CHANGE): can1: link becomes ready
[ 167.194387] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000004, rxerr 0, txerr 96, error type 0, pos 2, ALC id_field 0, bit 0
[ 167.207662] ctucanfd c0052000.ctu_can_fd can1: error_warning
```
EWL triggers when txerr reaches txerr limit. That's good.
```
[ 167.213520] ctucanfd c0052000.ctu_can_fd can1: ctucan_err_interrupt: ISR = 0x00000c10, rxerr 0, txerr 163, error type 2, pos 7, ALC id_field 0, bit 0
[ 167.226875] ctucanfd c0052000.ctu_can_fd can1: Fault conf: state = 1
[ 167.233394] ctucanfd c0052000.ctu_can_fd can1: error_warning, but ISR[FCSI] was set! (HW bug?)
[ 167.242331] ctucanfd c0052000.ctu_can_fd can1: error_warning
```
FCSI triggers, because txerr > 128. Then the controller should become ERROR-PASSIVE, but there is `Fault conf: state = 1`, which means ERROR-WARNING. This ERROR-WARNING state is returned by `ctucan_hw_read_error_state` function, that reads CTU_CAN_FD_EWL register and finds that `reg.s.era` is set. It shouldn't be, right?
Another matter is that when error counters fall down below the error warning limit, the EWLI should trigger too (but it doesn't), so driver can change back to ERROR-ACTIVE state.
##### Driver
I would then suggest to rewrite error interrupt handling in a way that FCSI and EWLI are handled together in one `if` block and get rid of the `error_warning, but ISR[FCSI] was set! (HW bug?)`. Or is there a reason to keep it separate?https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/329EWLI both ways2019-10-30T21:46:39ZIlle, Ondrej, Ing.EWLI both waysTrigger EWL Interrupt also when both TX, RX Error counters drop below the EWL.
This is needed by driver to properly return to Error Active state from Error
Warning state.Trigger EWL Interrupt also when both TX, RX Error counters drop below the EWL.
This is needed by driver to properly return to Error Active state from Error
Warning state.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/330Split register list from RTL2020-01-17T12:51:49ZIlle, Ondrej, Ing.Split register list from RTLRemove register list from RTL CAN_FD_Register_map and use it only for TB in standalone file.
Furthermore remove duplicity on t_memory_reg...Remove register list from RTL CAN_FD_Register_map and use it only for TB in standalone file.
Furthermore remove duplicity on t_memory_reg...https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/331TXBHC Interrupt in Bus-off2019-12-03T21:15:28ZIlle, Ondrej, Ing.TXBHC Interrupt in Bus-offCurrently when node is in Bus-off and TXT Buffer receives Set Ready command,
it moves to Ready and then immediately to TX Failed. But this transfer does
not invoke TXBHC Interrupt! This should be either noted in Datasheet,
or it should b...Currently when node is in Bus-off and TXT Buffer receives Set Ready command,
it moves to Ready and then immediately to TX Failed. But this transfer does
not invoke TXBHC Interrupt! This should be either noted in Datasheet,
or it should be implemented that TXBHCI is invoked!
The decision is that it will be implemented so that TXBHCI behaviour is
consistent!
Then CTU CAN FD driver will get TXBHCI when it is bus-off, and it should not
execute TXT Buffer priority rotation (to keep the TXT Buffer in
failed and not to move it for further transmission)... Or should it be rotated?https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/332Split driver into OF and PCI modules2019-12-02T21:10:55ZJaroslav BeranSplit driver into OF and PCI modulesDue to compile errors when both CONFIG_OF and CONFIG_PCI enabled with newer kernels, driver has to be split into two modules which are compiled separately.Due to compile errors when both CONFIG_OF and CONFIG_PCI enabled with newer kernels, driver has to be split into two modules which are compiled separately.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/333fix build issues2019-11-08T02:17:02ZIlle, Ondrej, Ing.fix build issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/334Explore coverage with single thread2020-01-03T11:09:03ZIlle, Ondrej, Ing.Explore coverage with single threadhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/335Update Vivado component after top level component change to can_top_apb2019-11-09T15:01:08ZPavel PisaUpdate Vivado component after top level component change to can_top_apbhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/336Feature tests extension2019-11-28T17:19:35ZIlle, Ondrej, Ing.Feature tests extensionImplement feature tests for the rest of the registers.Implement feature tests for the rest of the registers.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/337Resolve simulataneous SSP bit error capture and clear!2019-11-29T09:00:02ZIlle, Ondrej, Ing.Resolve simulataneous SSP bit error capture and clear!When SSP bit error is detected simultaneously with normal RX trigger,
it will probably happend that it will be ignored. Invoke this in
simulation and fix it.When SSP bit error is detected simultaneously with normal RX trigger,
it will probably happend that it will be ignored. Invoke this in
simulation and fix it.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/338Optimize auto-gate2020-01-18T21:20:35ZIlle, Ondrej, Ing.Optimize auto-gateOptimize Protocol control FSM not to use auto-gate to avoid long combinatorial paths!Optimize Protocol control FSM not to use auto-gate to avoid long combinatorial paths!https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/339Fix PSL coverage2019-12-02T22:44:59ZIlle, Ondrej, Ing.Fix PSL coveragePSL functional coverage must have "cover" with sequences, not with
logical operators only according to:
https://insights.sigasi.com/tech/psl.ebnf/#Sequence
New GHDL build does interpret this more strictly.PSL functional coverage must have "cover" with sequences, not with
logical operators only according to:
https://insights.sigasi.com/tech/psl.ebnf/#Sequence
New GHDL build does interpret this more strictly.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/340stat_bus[187] driven twice ... tx_trigger2019-12-06T23:39:55ZPavel Pisastat_bus[187] driven twice ... tx_trigger```
Error (10031): Net "stat_bus[187]" at can_core.vhd(1159) is already driven by input port "tx_trigger", and cannot be driven by another signal File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_core/can_cor...```
Error (10031): Net "stat_bus[187]" at can_core.vhd(1159) is already driven by input port "tx_trigger", and cannot be driven by another signal File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_core/can_core.vhd Line: 1159
Error (10032): "tx_trigger" was declared at can_core.vhd(234) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_core/can_core.vhd Line: 234
Error (12152): Can't elaborate user hierarchy "can_top_level:\can_fd_instances_for:0:can_fd_inst|can_core:can_core_inst" File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_top_level.vhd Line: 755
```
List of warnings, many PCIe related/unrelated to CTU CAN FD IP core
```
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_hard_ip_0: Module dependency loop involving: "pcie_internal_hip" (altera_pcie_internal_hard_ip_qsys 17.0)
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_hard_ip_0: Module dependency loop involving: "avalon_clk" (altera_clock_bridge 17.0), "pcie_internal_hip" (altera_pcie_internal_hard_ip_qsys 17.0)
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip.app_msi_ack: Interface has no signals
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip.app_msi_num: Interface has no signals
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip.app_msi_req: Interface has no signals
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip.test_out_export: Interface has no signals
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.pcie_core_clk cannot be both connected and exported
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.app_msi_ack must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.rc_rx_analogreset must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.rc_rx_digitalreset must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.app_msi_num must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.app_msi_req must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.msi_interface_export must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.tx_deemph_0 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.tx_margin_0 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pcie_internal_hip: pcie_internal_hip.test_out_export must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pipe_interface_internal: pipe_interface_internal.pll_powerdown_pcs must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pipe_interface_internal: pipe_interface_internal.rateswitch_pcs must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.pipe_interface_internal: pipe_interface_internal.rateswitchbaseclock_pcs must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_2 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_3 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_4 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_5 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_6 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_7 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_8 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.refclk_conduit: refclk_conduit.conduit_out_9 must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0.reset_controller_internal: reset_controller_internal.reset_n_out cannot be both connected and exported
Warning (12251): Pcie_core.altpll_0: altpll_0.areset_conduit must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.altpll_0: altpll_0.locked_conduit must be exported, or connected to a matching conduit.
Warning (12251): Pcie_core.pcie_hard_ip_0: Interrupt sender pcie_hard_ip_0.cra_irq is not connected to an interrupt receiver
Warning (12251): Pcie_core.altpll_0: altpll_0.pll_slave must be connected to an Avalon-MM master
Warning (12251): Pcie_core.pcie_hard_ip_0: pcie_hard_ip_0.txs must be connected to an Avalon-MM master
Warning (12018): Entity "dff" will be ignored because it conflicts with Quartus Prime primitive name File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/common/dff.vhd Line: 50
Warning (10885): Verilog HDL Attribute warning at altera_pcie_hard_ip_reset_controller.v(79): synthesis attribute "ALTERA_ATTRIBUTE" with value ""SUPPRESS_DA_RULE_INTERNAL=R102"" has no object and is ignored File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 79
Warning (10885): Verilog HDL Attribute warning at altera_pcie_hard_ip_reset_controller.v(80): synthesis attribute "ALTERA_ATTRIBUTE" with value ""SUPPRESS_DA_RULE_INTERNAL=R102"" has no object and is ignored File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 80
Warning (10236): Verilog HDL Implicit Net warning at altera_pcie_hard_ip_reset_controller.v(262): created implicit net for "pipe_mode_int" File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 262
Warning (10236): Verilog HDL Implicit Net warning at altpciexpav_stif_app.v(676): created implicit net for "txrp_tlp_ack" File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_app.v Line: 676
Warning (10540): VHDL Signal Declaration warning at db4cgx15_pcie_ctu_can_fd.vhd(79): used explicit default value for signal "can_fd_local_feedback" because signal was never assigned a value File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db4cgx15_pcie_ctu_can_fd.vhd Line: 79
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(801): object pm_event_sopc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 801
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(803): object pme_to_cr_sopc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 803
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(817): object sopc_dlctrllink2 used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 817
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(818): object sopc_dldataupfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 818
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(819): object sopc_dlhdrupfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 819
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(820): object sopc_dlinhdllp used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 820
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(821): object sopc_dlreqphycfg used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 821
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(822): object sopc_dlreqphypm used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 822
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(823): object sopc_dlrequpfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 823
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(824): object sopc_dlreqwake used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 824
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(825): object sopc_dlrxecrcchk used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 825
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(826): object sopc_dlsndupfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 826
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(827): object sopc_dltxcfgextsy used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 827
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(828): object sopc_dltxreqpm used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 828
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(829): object sopc_dltxtyppm used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 829
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(830): object sopc_dltypupfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 830
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(831): object sopc_dlvcidmap used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 831
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(832): object sopc_dlvcidupfc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 832
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(838): object swdn_in_sopc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 838
Warning (10858): Verilog HDL warning at altpcie_hip_pipen1b_qsys.v(840): object swup_in_sopc used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_hip_pipen1b_qsys.v Line: 840
Warning (10230): Verilog HDL assignment warning at altpcie_pcie_reconfig_bridge.v(236): truncated value with size 32 to match size of target (7) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pcie_reconfig_bridge.v Line: 236
Warning (10230): Verilog HDL assignment warning at altpcie_pcie_reconfig_bridge.v(242): truncated value with size 32 to match size of target (7) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pcie_reconfig_bridge.v Line: 242
Warning (10230): Verilog HDL assignment warning at altpcie_pcie_reconfig_bridge.v(368): truncated value with size 32 to match size of target (5) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pcie_reconfig_bridge.v Line: 368
Warning (10230): Verilog HDL assignment warning at altpcie_pcie_reconfig_bridge.v(369): truncated value with size 32 to match size of target (5) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pcie_reconfig_bridge.v Line: 369
Warning (10230): Verilog HDL assignment warning at altpcie_pcie_reconfig_bridge.v(381): truncated value with size 32 to match size of target (8) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pcie_reconfig_bridge.v Line: 381
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_app.v(270): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_app.v Line: 270
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_rx_cntrl.v(289): object "rx_eop_reg" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_rx_cntrl.v Line: 289
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_rx_cntrl.v(1030): truncated value with size 32 to match size of target (6) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_rx_cntrl.v Line: 1030
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_a2p_fixtrans.v(158): truncated value with size 32 to match size of target (4) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_a2p_fixtrans.v Line: 158
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_a2p_fixtrans.v(174): truncated value with size 32 to match size of target (4) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_a2p_fixtrans.v Line: 174
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(268): object "addr_hi" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 268
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(285): object "nph_cred_sub" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 285
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(295): object "txrp_eop" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 295
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(298): object "is_rp_wr" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 298
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(301): object "rp_tlp_sop" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 301
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_tx_cntrl.v(302): object "rp_tlp_eop" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 302
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_tx_cntrl.v(1043): truncated value with size 32 to match size of target (10) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_tx_cntrl.v Line: 1043
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_control_register.v(167): object "rp_tx_fifo_full" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_control_register.v Line: 167
Warning (272007): Ignoring parameter INDATA_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_mailbox.v Line: 243
Warning (272007): Ignoring parameter WRCONTROL_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_mailbox.v Line: 243
Warning (272007): Ignoring parameter ADDRESS_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_mailbox.v Line: 243
Warning (287001): Assertion warning: Ignoring parameter INDATA_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/altsyncram_1sc1.tdf Line: 789
Warning (287001): Assertion warning: Ignoring parameter WRCONTROL_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/altsyncram_1sc1.tdf Line: 792
Warning (287001): Assertion warning: Ignoring parameter ADDRESS_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone IV GX of altsyncram megafunction cannot use input registers with clear signals File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/altsyncram_1sc1.tdf Line: 795
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_cr_interrupt.v(169): object "avl_irq_reg" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 169
Warning (10036): Verilog HDL or VHDL warning at altpciexpav_stif_cr_interrupt.v(196): object "PciComp_Stat_Reg_q2" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 196
Warning (10858): Verilog HDL warning at altpciexpav_stif_cr_interrupt.v(220): object legacy_irq_req used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 220
Warning (10858): Verilog HDL warning at altpciexpav_stif_cr_interrupt.v(221): object legacy_irq_req_reg used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 221
Warning (10858): Verilog HDL warning at altpciexpav_stif_cr_interrupt.v(223): object rp_rxcpl_received used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 223
Warning (10858): Verilog HDL warning at altpciexpav_stif_cr_interrupt.v(224): object rp_rxcpl_received_reg used but never assigned File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cr_interrupt.v Line: 224
Warning (10230): Verilog HDL assignment warning at altpciexpav_stif_cfg_status.v(181): truncated value with size 40 to match size of target (32) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpciexpav_stif_cfg_status.v Line: 181
Warning (10034): Output port "rx_patterndetect[0]" at pcie_core_pcie_hard_ip_0_altgx_internal.v(106) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/pcie_core_pcie_hard_ip_0_altgx_internal.v Line: 106
Warning (10034): Output port "rx_syncstatus[0]" at pcie_core_pcie_hard_ip_0_altgx_internal.v(107) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/pcie_core_pcie_hard_ip_0_altgx_internal.v Line: 107
Warning (10036): Verilog HDL or VHDL warning at altera_pcie_hard_ip_reset_controller.v(262): object "pipe_mode_int" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 262
Warning (10036): Verilog HDL or VHDL warning at altera_pcie_hard_ip_reset_controller.v(90): object "test_sim" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 90
Warning (10230): Verilog HDL assignment warning at altera_pcie_hard_ip_reset_controller.v(153): truncated value with size 32 to match size of target (11) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 153
Warning (10030): Net "clk250_out" at altera_pcie_hard_ip_reset_controller.v(67) has no driver or initial value, using a default initial value '0' File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 67
Warning (10030): Net "clk500_out" at altera_pcie_hard_ip_reset_controller.v(68) has no driver or initial value, using a default initial value '0' File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 68
Warning (10034): Output port "clk125_export" at altera_pcie_hard_ip_reset_controller.v(72) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_pcie_hard_ip_reset_controller.v Line: 72
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(284): truncated value with size 32 to match size of target (8) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 284
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(285): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 285
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(286): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 286
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(287): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 287
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(288): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 288
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(289): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 289
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(290): truncated value with size 32 to match size of target (2) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 290
Warning (10230): Verilog HDL assignment warning at altpcie_pipe_interface.v(459): truncated value with size 32 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 459
Warning (10034): Output port "txdata1_ext" at altpcie_pipe_interface.v(78) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 78
Warning (10034): Output port "txdata2_ext" at altpcie_pipe_interface.v(79) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 79
Warning (10034): Output port "txdata3_ext" at altpcie_pipe_interface.v(80) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 80
Warning (10034): Output port "txdata4_ext" at altpcie_pipe_interface.v(81) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 81
Warning (10034): Output port "txdata5_ext" at altpcie_pipe_interface.v(82) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 82
Warning (10034): Output port "txdata6_ext" at altpcie_pipe_interface.v(83) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 83
Warning (10034): Output port "txdata7_ext" at altpcie_pipe_interface.v(84) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 84
Warning (10034): Output port "rxpolarity1_ext" at altpcie_pipe_interface.v(131) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 131
Warning (10034): Output port "rxpolarity2_ext" at altpcie_pipe_interface.v(132) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 132
Warning (10034): Output port "rxpolarity3_ext" at altpcie_pipe_interface.v(133) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 133
Warning (10034): Output port "rxpolarity4_ext" at altpcie_pipe_interface.v(134) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 134
Warning (10034): Output port "rxpolarity5_ext" at altpcie_pipe_interface.v(135) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 135
Warning (10034): Output port "rxpolarity6_ext" at altpcie_pipe_interface.v(136) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 136
Warning (10034): Output port "rxpolarity7_ext" at altpcie_pipe_interface.v(137) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 137
Warning (10034): Output port "txcompl1_ext" at altpcie_pipe_interface.v(151) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 151
Warning (10034): Output port "txcompl2_ext" at altpcie_pipe_interface.v(152) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 152
Warning (10034): Output port "txcompl3_ext" at altpcie_pipe_interface.v(153) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 153
Warning (10034): Output port "txcompl4_ext" at altpcie_pipe_interface.v(154) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 154
Warning (10034): Output port "txcompl5_ext" at altpcie_pipe_interface.v(155) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 155
Warning (10034): Output port "txcompl6_ext" at altpcie_pipe_interface.v(156) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 156
Warning (10034): Output port "txcompl7_ext" at altpcie_pipe_interface.v(157) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 157
Warning (10034): Output port "txdatak1_ext" at altpcie_pipe_interface.v(171) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 171
Warning (10034): Output port "txdatak2_ext" at altpcie_pipe_interface.v(172) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 172
Warning (10034): Output port "txdatak3_ext" at altpcie_pipe_interface.v(173) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 173
Warning (10034): Output port "txdatak4_ext" at altpcie_pipe_interface.v(174) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 174
Warning (10034): Output port "txdatak5_ext" at altpcie_pipe_interface.v(175) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 175
Warning (10034): Output port "txdatak6_ext" at altpcie_pipe_interface.v(176) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 176
Warning (10034): Output port "txdatak7_ext" at altpcie_pipe_interface.v(177) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 177
Warning (10034): Output port "txelecidle1_ext" at altpcie_pipe_interface.v(203) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 203
Warning (10034): Output port "txelecidle2_ext" at altpcie_pipe_interface.v(204) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 204
Warning (10034): Output port "txelecidle3_ext" at altpcie_pipe_interface.v(205) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 205
Warning (10034): Output port "txelecidle4_ext" at altpcie_pipe_interface.v(206) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 206
Warning (10034): Output port "txelecidle5_ext" at altpcie_pipe_interface.v(207) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 207
Warning (10034): Output port "txelecidle6_ext" at altpcie_pipe_interface.v(208) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 208
Warning (10034): Output port "txelecidle7_ext" at altpcie_pipe_interface.v(209) has no driver File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altpcie_pipe_interface.v Line: 209
Warning (10230): Verilog HDL assignment warning at altera_merlin_burst_adapter_13_1.sv(790): truncated value with size 10 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_burst_adapter_13_1.sv Line: 790
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 283
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 742
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 743
Warning (10230): Verilog HDL assignment warning at altera_merlin_burst_adapter_13_1.sv(790): truncated value with size 10 to match size of target (1) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_burst_adapter_13_1.sv Line: 790
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object "in_write" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 283
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object "aligned_addr" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 742
Warning (10036): Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object "aligned_byte_cnt" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/db4cgx15_pcie_ctu_can_fd/db/ip/pcie_core/submodules/altera_merlin_width_adapter.sv Line: 743
Warning (10036): Verilog HDL or VHDL warning at can_top_level.vhd(469): object "bt_fsm" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_top_level.vhd Line: 469
Warning (10036): Verilog HDL or VHDL warning at can_top_level.vhd(472): object "tq_edge" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_top_level.vhd Line: 472
Warning (10540): VHDL Signal Declaration warning at memory_registers.vhd(340): used explicit default value for signal "buf_addr" because signal was never assigned a value File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/memory_registers/memory_registers.vhd Line: 340
Warning (10873): Using initial value X (don't care) for net "Control_registers_in.rec[15..9]" at memory_registers.vhd(238) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/memory_registers/memory_registers.vhd Line: 238
Warning (10873): Using initial value X (don't care) for net "Control_registers_in.tec[15..9]" at memory_registers.vhd(238) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/memory_registers/memory_registers.vhd Line: 238
Warning (10873): Using initial value X (don't care) for net "Control_registers_in.trv_delay[15..7]" at memory_registers.vhd(238) File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/memory_registers/memory_registers.vhd Line: 238
Warning (10036): Verilog HDL or VHDL warning at rx_buffer_fsm.vhd(139): object "drv_rtsopt" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/rx_buffer/rx_buffer_fsm.vhd Line: 139
Warning (10036): Verilog HDL or VHDL warning at rx_buffer_fsm.vhd(149): object "cmd_join" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/rx_buffer/rx_buffer_fsm.vhd Line: 149
Warning (10036): Verilog HDL or VHDL warning at can_core.vhd(357): object "crc_src" assigned a value but never read File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/modules/ctu_can_fd/src/can_core/can_core.vhd Line: 357
```Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/341Port direction mismatch2019-12-06T07:52:49ZIlle, Ondrej, Ing.Port direction mismatchhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/342Debug nightly run2019-12-06T12:36:12ZIlle, Ondrej, Ing.Debug nightly runhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/343PCI driver exception when signature not found.2019-12-09T12:59:36ZPavel PisaPCI driver exception when signature not found.When core is reload but PCI bus is not scanned again then reads from stale regions return 0xff.
Return value of ctucan_probe_common() does not return negative value in such case which leads
to attmpt to setup multiple instances.When core is reload but PCI bus is not scanned again then reads from stale regions return 0xff.
Return value of ctucan_probe_common() does not return negative value in such case which leads
to attmpt to setup multiple instances.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/344Update Debian DKMS driver package for separated PCI module.2019-12-09T16:04:43ZPavel PisaUpdate Debian DKMS driver package for separated PCI module.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/345Include driver documentation from Martin Jerabek's theses.2019-12-10T08:30:28ZPavel PisaInclude driver documentation from Martin Jerabek's theses.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/346Include check_path in linux driver build2019-12-13T15:10:14ZIlle, Ondrej, Ing.Include check_path in linux driver buildhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/347Update driver documentation and Jaroslav Beran copyright.2019-12-12T16:48:24ZPavel PisaUpdate driver documentation and Jaroslav Beran copyright.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/348Driver documentation acknowledge the project funding2019-12-18T06:07:20ZPavel PisaDriver documentation acknowledge the project fundingPavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/349Documentation clarification of TXCE in section 3.1.38 of Progdokum.pdf2020-01-08T18:57:23ZJan CharvátDocumentation clarification of TXCE in section 3.1.38 of Progdokum.pdfTXCE Activates "set_empty" command. Transits frone TX Done, TX Error or TX Aborted to Done.
It should be Empty instead of Done.TXCE Activates "set_empty" command. Transits frone TX Done, TX Error or TX Aborted to Done.
It should be Empty instead of Done.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/350Improve readme2020-01-13T19:42:05ZIlle, Ondrej, Ing.Improve readmehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/351Resolve synthesis warnings2020-03-27T11:18:58ZIlle, Ondrej, Ing.Resolve synthesis warningsResolve warnings from Xilinx VivadoResolve warnings from Xilinx Vivadohttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/352Simultaneous RRS=1 and FDF2020-04-04T12:58:09ZIlle, Ondrej, Ing.Simultaneous RRS=1 and FDFAccording to ISO TC 7.1.4 IUT shall be able to receive CAN FD frame where RRS bit is high.
In current implementation RTR flag is sampled in position of RRS bit and this is used to decide
that no data field will be contained in that fram...According to ISO TC 7.1.4 IUT shall be able to receive CAN FD frame where RRS bit is high.
In current implementation RTR flag is sampled in position of RRS bit and this is used to decide
that no data field will be contained in that frame (as if RTR frame). In case of CAN FD frame
(FDF = 1), this information shall be ignored however.ISO conformance testinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/353Split Err_Ovr_delim_too_long2020-10-31T21:16:26ZIlle, Ondrej, Ing.Split Err_Ovr_delim_too_longPC FSM state indicating Error / Overload delimiter is too long is common for both Error flag and Overload flag.
After this state, PC FSM goes to Error delimiter regardless of the fact whether this was Error or Overload flag!
In this sta...PC FSM state indicating Error / Overload delimiter is too long is common for both Error flag and Overload flag.
After this state, PC FSM goes to Error delimiter regardless of the fact whether this was Error or Overload flag!
In this state, even after too long Overload delimiter, device will signal that DUT is transmitting Error frame (which
is not true) in status registers.
Strictly speaking this does not mind, because behaviour of DUT with respect to standard is met (in both cases error counters
are incremented accordingly) -> TODO: What if device is not transmitter nor receiver in case of overload flag? Can this happen?
This should be resolved like so:
1. [ ] Create two PC fsm states for too long flag (Overload/Error)
2. [ ] Describe changes in PC FSM diagram in spec.
The behaviour of overload too long will be nearly the same as Error too long, with following differences:
1. Error will signal Error frame is transmitted, Overload will signal overload is transmitted.
2. After this states ends, Error too long will go to error delimiter, Overload will go to overload delimiter.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/354Fix Overload delimiter lenght2020-04-14T17:52:10ZIlle, Ondrej, Ing.Fix Overload delimiter lenghtOverload delimiter should have length of 8 bits, not 7!Overload delimiter should have length of 8 bits, not 7!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/355Fix REC decrement2020-04-17T19:39:42ZIlle, Ondrej, Ing.Fix REC decrementAccording to ISO11898-1:2015 REC shall be decremented by 1 upon succesfull reception of frame. This means up to succesfull transmission of ACK bit!
This point in CAN frame is different than Frame validation which is one bit before end of...According to ISO11898-1:2015 REC shall be decremented by 1 upon succesfull reception of frame. This means up to succesfull transmission of ACK bit!
This point in CAN frame is different than Frame validation which is one bit before end of EOF! This means that Frame can be
"succesfully received", REC decremented (after ACK) and e.g. form error occuring in first bit of EOF causing the frame not to
be validated (no valid reception will be signaled, no frame will be stored in RX Buffer)!
In CTU CAN FD, the moment of REC decrement is the same as the moment of frame validation and that is last bit of EOF.
7.6.7 of ISO16845-1 2016 is specifically designed to catch this issue as it expects first decrement of REC after ACK and then increment by 1 due to form error on ACK delimiter, thus leaving REC unchanged after the frame is over!
In current implementation of CTU CAN FD the point of decrement will never occur, and REC will only be incremented. This is a bug.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/356Documentation review2020-04-18T18:04:49ZIlle, Ondrej, Ing.Documentation reviewhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/357Non-synchronisation on dominant transmitted bit2020-05-06T19:40:16ZIlle, Ondrej, Ing.Non-synchronisation on dominant transmitted bitAn exception to re-synchronisation rule is not to perform resync with positive phase error
when node does transmitt dominant bit.
In current implementation, this exception is driven in protcol control fsm when
node is transmitter and it...An exception to re-synchronisation rule is not to perform resync with positive phase error
when node does transmitt dominant bit.
In current implementation, this exception is driven in protcol control fsm when
node is transmitter and it does transmit dominant bit.
This however does not cover all cases of dominant bit transmission! E.g. when node
transmitts an error frame it also does transmitt dominant bit (it does not even have
to be transmitter) and it should NOT perform positive resynchronisation!
This should be fixed although there is no test for this in compliance sequence
(if e.g. node is receiver).ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/358Protocol exception feature test2021-02-18T22:16:02ZIlle, Ondrej, Ing.Protocol exception feature testAdd Protocol exception test to verify all combinations of Protocol exception.
This includes following:
1. CAN 2.0 - no protocol exception
2. CAN FD Tolerant - protocol exception on Recessive FDF.
3. CAN FD Enabled - no protocol exception...Add Protocol exception test to verify all combinations of Protocol exception.
This includes following:
1. CAN 2.0 - no protocol exception
2. CAN FD Tolerant - protocol exception on Recessive FDF.
3. CAN FD Enabled - no protocol exception - form error on recessive r0 in CAN FD frames.
4. CAN FD Enabled - protocol exception on Recessive r0 in FD frames.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/359Prescaler bug-fixes2020-05-23T09:31:40ZIlle, Ondrej, Ing.Prescaler bug-fixesFollowing issues should be resolved in prescaler:
1. [x] When detecting negative phase error should there be a -1 in calculation?
2. [x] When detective negative resynchronisation with phase error <=Following issues should be resolved in prescaler:
1. [x] When detecting negative phase error should there be a -1 in calculation?
2. [x] When detective negative resynchronisation with phase error <=ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/360Fix TX/RX simultaneous trigger2020-07-09T13:46:25ZIlle, Ondrej, Ing.Fix TX/RX simultaneous triggerIf PH2 is shortened to 0, prescaler trigger_generator module shall delay consecutive TX trigger
by 1 clock cycle. This is not working properly, fix this.If PH2 is shortened to 0, prescaler trigger_generator module shall delay consecutive TX trigger
by 1 clock cycle. This is not working properly, fix this.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/361VHDL 93 with Vivado compatibility troubles: rx_triggers cannot read from output2020-07-22T07:26:34ZPavel PisaVHDL 93 with Vivado compatibility troubles: rx_triggers cannot read from output```
ERROR: [Synth 8-1779] cannot read from 'out' object rx_triggers ; use 'buffer' or 'inout' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/prescaler/trigger_generat
or.vhd:194]
INFO: [Synth 8-2810] unit rtl igno...```
ERROR: [Synth 8-1779] cannot read from 'out' object rx_triggers ; use 'buffer' or 'inout' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/prescaler/trigger_generat
or.vhd:194]
INFO: [Synth 8-2810] unit rtl ignored due to previous errors [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/prescaler/trigger_generator.vhd:134]
```
Problem seems to be already solved in bf1936eb848f509ea4ade0abf421629b7fc58c85 on 199-iso-testbench.
The problem prevents build and test on Zynq, @illeondr, please, consider moving of src: patches to the master. https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/362Byte order of CAN farme data is wappped on big-endian system.2020-07-25T12:12:32ZPavel PisaByte order of CAN farme data is wappped on big-endian system.This problem can be solved in hardware or in the driver. Change in the driver is the right solution.
Hardware swap for all word size registers would lead to inconsistency in the fields which are not byte wide.
Change in only can frame re...This problem can be solved in hardware or in the driver. Change in the driver is the right solution.
Hardware swap for all word size registers would lead to inconsistency in the fields which are not byte wide.
Change in only can frame related data in the Tx frame buffers is feasible and eliminates one bswap32 in the software. Change in Rx FIFO would require to store data byte swapped into FIFO because dynamically change read word endiannesss on the register read size according to read of metadata and actual data is problematic.
All these options are complicated and if there is no option to switch runtime order between byte data and wider registers dynamically then there is no feasible option to build PCI card which can work correctly in both, big-endian and little-endian systems.
Software side swap is relatively cheap on today CPU architectures. What is the best solution for DMA in future is questionable because SocketCAN does not define fixed byte order for identifier.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/363ci: driver build fails after makefile relaxed to easier use on multiple archi...2020-07-25T23:31:35ZPavel Pisaci: driver build fails after makefile relaxed to easier use on multiple architectures.When KDIR is specified then new version does not enforce
ARM target build because it complicates MIPS and native builds.
But when the Linux kernel build directory does not contain
GNUmakefile trick to setup ARCH and CROSS_COMPILE, then
p...When KDIR is specified then new version does not enforce
ARM target build because it complicates MIPS and native builds.
But when the Linux kernel build directory does not contain
GNUmakefile trick to setup ARCH and CROSS_COMPILE, then
plain make with KDIR fails after relaxation.
Specification of the ARM target explicitly in CI command
is required now.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/364driver: build native driver for current running kernel by default2020-07-28T07:21:05ZPavel Pisadriver: build native driver for current running kernel by defaultWhen no parameter or environment variable is set then build
driver for current running Linux kernel.When no parameter or environment variable is set then build
driver for current running Linux kernel.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/365driver: fix long ago omitted byte swap in bing-endian register write.2020-07-28T11:06:36ZPavel Pisadriver: fix long ago omitted byte swap in bing-endian register write.Even on big-endian systems ioread32/iowrite32 accesses memory-mapped
register in little-endian manner to be compatible with PCI devices
so the problem of missing be in iowrite32be for ctucan_hw_write32_be
has not been found during MIPS M...Even on big-endian systems ioread32/iowrite32 accesses memory-mapped
register in little-endian manner to be compatible with PCI devices
so the problem of missing be in iowrite32be for ctucan_hw_write32_be
has not been found during MIPS Malta QEMU test, but it should be
corrected for case of native CTU CAN FD core mapping on big-endian
systems.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/366doc: mention CTU CAN FD QEMU emulation support and more people support2020-07-28T11:45:06ZPavel Pisadoc: mention CTU CAN FD QEMU emulation support and more people supporthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/367driver: source formatting to silence most of the 5.4 Linux kernel checkpatch ...2020-08-02T20:35:00ZPavel Pisadriver: source formatting to silence most of the 5.4 Linux kernel checkpatch reported problemshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/368driver: updates based on v4 patches review2020-08-15T19:00:15ZPavel Pisadriver: updates based on v4 patches reviewUpdate to incorporate next review responses
[PATCH v4 0/6] CTU CAN FD open-source IP core SocketCAN driver, PCI, platform integration and documentation
* Jakub Kicinski https://lkml.org/lkml/2020/8/3/1188
[PATCH v4 2/6] dt-bindings: ne...Update to incorporate next review responses
[PATCH v4 0/6] CTU CAN FD open-source IP core SocketCAN driver, PCI, platform integration and documentation
* Jakub Kicinski https://lkml.org/lkml/2020/8/3/1188
[PATCH v4 2/6] dt-bindings: net: can: binding for CTU CAN FD open-source IP core.
* Pavel Machek https://lkml.org/lkml/2020/8/4/253
* Pavel Machek https://lkml.org/lkml/2020/8/4/261
* Rob Herring https://lkml.org/lkml/2020/8/6/304
* Rob Herring https://lkml.org/lkml/2020/8/6/333
[PATCH v4 3/6] can: ctucanfd: add support for CTU CAN FD open-source IP core - bus independent part.
* Pavel Machek https://lkml.org/lkml/2020/8/4/291
[PATCH v4 4/6] can: ctucanfd: CTU CAN FD open-source IP core - PCI bus support.
* Randy Dunlap https://lkml.org/lkml/2020/8/3/1122https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/369Source code decoupling2020-09-15T15:43:54ZIlle, Ondrej, Ing.Source code decouplingTo make design + TB more modular, following can be done:
1. [x] Split VHDL sources into TB and RTL libraries, avoid using implicit "work" library.
2. [ ] Provide VUnit replacement package, which would allow running TBs also without Vunit.To make design + TB more modular, following can be done:
1. [x] Split VHDL sources into TB and RTL libraries, avoid using implicit "work" library.
2. [ ] Provide VUnit replacement package, which would allow running TBs also without Vunit.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/370Split sources into two libs2020-09-15T15:41:21ZIlle, Ondrej, Ing.Split sources into two libsTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/371Bus-off management2020-10-31T21:45:01ZIlle, Ondrej, Ing.Bus-off managementIt might be good to add option which will keep TXT Buffers in Ready state when node
goes to bus-off (instead of going to TX failed). This could be a configurable option
in MODE register.It might be good to add option which will keep TXT Buffers in Ready state when node
goes to bus-off (instead of going to TX failed). This could be a configurable option
in MODE register.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/372Reintegration - counter clear!2020-10-11T14:59:51ZIlle, Ondrej, Ing.Reintegration - counter clear!According to ISO spec, CAN FD enabled node shall restart integration/reintegration counter shall be restarted
when there is a synchronisation edge! At the moment, CTU CAN FD does not implement this feature. This shall
be implemented.According to ISO spec, CAN FD enabled node shall restart integration/reintegration counter shall be restarted
when there is a synchronisation edge! At the moment, CTU CAN FD does not implement this feature. This shall
be implemented.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/373Test framework cleanup2020-09-20T14:58:37ZIlle, Ondrej, Ing.Test framework cleanupAs most of the tests were re-written and RTL changed extensively, conversions of TCL
files to GHW files with TCL parser is not needed anymore. The aim of this task is to
remove it.As most of the tests were re-written and RTL changed extensively, conversions of TCL
files to GHW files with TCL parser is not needed anymore. The aim of this task is to
remove it.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/374Testbench unification2021-04-23T20:59:39ZIlle, Ondrej, Ing.Testbench unificationAt the moment, there are several different testbenches for CTU CAN FD:
Unit tests - each own TB
Feature - One TB, many tests
Sanity - One TB, no tests
Reference - One TB, different tests based on data sets.
Compliance - One TB,...At the moment, there are several different testbenches for CTU CAN FD:
Unit tests - each own TB
Feature - One TB, many tests
Sanity - One TB, no tests
Reference - One TB, different tests based on data sets.
Compliance - One TB, different tests.
The aim of this task is to merge Feature, Reference and Compliance tests into
a single TB, this would be then the main TB of CTU CAN FD. Unit and Sanity tests
can be kept separate.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/375Vivado component build broken by reference to ctu_can_fd_rtl library intead o...2020-09-30T14:56:35ZPavel PisaVivado component build broken by reference to ctu_can_fd_rtl library intead of work automatic selfreference.The separation of libraries to ctu_can_fd_rtl and ctu_can_fd_tb
```
-Library work;
-use work.id_transfer.all;
...
+Library ctu_can_fd_rtl;
+use ctu_can_fd_rtl.id_transfer.all;
...
```
breaks Vivado build using based on CTU_CAN_FD_1_0 c...The separation of libraries to ctu_can_fd_rtl and ctu_can_fd_tb
```
-Library work;
-use work.id_transfer.all;
...
+Library ctu_can_fd_rtl;
+use ctu_can_fd_rtl.id_transfer.all;
...
```
breaks Vivado build using based on CTU_CAN_FD_1_0 component.
```
ERROR: [Synth 8-4169] error in use clause: package 'id_transfer' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/bus
_sampling/bit_err_detector.vhd:59]
ERROR: [Synth 8-4169] error in use clause: package 'can_constants' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/b
us_sampling/bit_err_detector.vhd:60]
ERROR: [Synth 8-4169] error in use clause: package 'can_components' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/
bus_sampling/bit_err_detector.vhd:61]
ERROR: [Synth 8-4169] error in use clause: package 'can_types' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/bus_s
ampling/bit_err_detector.vhd:62]
ERROR: [Synth 8-4169] error in use clause: package 'cmn_lib' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/bus_sam
pling/bit_err_detector.vhd:63]
ERROR: [Synth 8-4169] error in use clause: package 'drv_stat_pkg' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/bu
s_sampling/bit_err_detector.vhd:64]
ERROR: [Synth 8-4169] error in use clause: package 'reduce_lib' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/d52f/bus_
sampling/bit_err_detector.vhd:65]
ERROR: [Synth 8-4169] error in use clause: package 'can_fd_register_map' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/
d52f/bus_sampling/bit_err_detector.vhd:67]
ERROR: [Synth 8-4169] error in use clause: package 'can_fd_frame_format' not found in library 'ctu_can_fd_rtl' [/builds/canbus/zynq/zynq-can-sja1000-top/system/src/top/ipshared/
d52f/bus_sampling/bit_err_detector.vhd:68]
```
I am not sure about the best solution. Inside library, the reference to itself can still use work, because work is a keyword. Some more discussion on a Vivado discussion pages
https://forums.xilinx.com/t5/Design-Entry/VHDL-Package-in-Vivado/td-p/835945
Other Vivado library discussion
https://forums.xilinx.com/t5/Synthesis/Using-libraries-in-Vivado/td-p/816436
Quartus/Intel FPGA tools build accepts library reference to its actual name without any issue.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/376TEC increment after ACK error in Error Passive state2020-10-07T16:43:40ZIlle, Ondrej, Ing.TEC increment after ACK error in Error Passive stateAccording to ISO 11898-1 2015 TEC shall be incremented if transmitter sends an error frame.
This has following exception:
If the transmitter is error-passive and detects an ACK error because of not detecting a dominant
ACK and does not...According to ISO 11898-1 2015 TEC shall be incremented if transmitter sends an error frame.
This has following exception:
If the transmitter is error-passive and detects an ACK error because of not detecting a dominant
ACK and does not detect a dominant bit while sending its passive error flag.
However, the current implementation is only looking at ACK error in passive error state! it does
NOT at all consider the second part of the exception. Test 8.6.18 is specifically designed to
detect this situation.
The behavior shall be following:
If there is dominant bit detected during passive error flag and it DUT detects dominant bit, it shall
not detect bit error nor increment error counter.
However, if ACK Error occured in Error Passive state and DUT starts transmitting passive error
flag due to this ACK error, then receiving dominant bit during consecutive passive error flag shall lead to
increment of TEC by 8!
So this is exception in TEC increment during passive error flag. Error frame probably still does
not have to be retransmitted, only TEC shall be incremented!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/377Passive Error flag - possible bug2020-10-01T22:38:56ZIlle, Ondrej, Ing.Passive Error flag - possible bugISO 11898-1 2015 states:
Passive error flags initiated by receivers shall not be able to prevail over any activity on the bus.
Therefore, error-passive receivers shall always wait for 6 subsequent equal bits after detecting an error
con...ISO 11898-1 2015 states:
Passive error flags initiated by receivers shall not be able to prevail over any activity on the bus.
Therefore, error-passive receivers shall always wait for 6 subsequent equal bits after detecting an error
condition. The passive error flag is complete when these 6 equal bits have been detected.
This is currently not the case with CTU CAN FD. Error passive receivers who transmitt passive error flag
will simply go on, transmitt passive error flag and after passive error flag wait for recessive bit
(as also with Active Error flag). No counting of 6 consecutive bits of equal value is done! Also,
ISO compliance test which tests this (7.5.1) does not reveal this issue, because it super-imposes passive
error flag with active error flag. Therefore CTU CAN FD will finish passive error flag sooner than it has
detected 6 consecutive bits of equal polarity, but it will wait on recessive bit before proceeding with
error delimiter. So the incorrect behavior is not revealed by the test.
If we consider following:
Error passive CTU CAN FD detects error as receiver and transmitts passive error flag. No other nodes see
any error, so they continue transmitting. No bit error is detected by CTU CAN FD, since reception of dominant
bits during passive error flag does not cause bit error. CTU CAN FD finishes its passive error flag and
detects recessive bit in coincidence with some transmitted bit by other nodes. Therefore CTU CAN FD proceeds
to error delimiter! Other nodes are still in their regular frame transmission. During error delimiter, CTU
CAN FD will detect form error, because other nodes will transmit at least one dominant bit due to bit stuffing.
So CTU CAN FD will restart next passive error flag and have un-wanted increments of REC!
Note: Probably 7.5.5 will detect this issue!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/378CRC Error in CAN FD Frames2020-10-06T18:24:14ZIlle, Ondrej, Ing.CRC Error in CAN FD FramesReceiver of CAN FD frame shall accept two recessive bits as ACK.
If receiver of CAN FD frame detect CRC error it shall signal it at first bit of EOF.
This means that during waiting it accepts CRC Delim + 2 ACK bits + ACK delim. Therefore...Receiver of CAN FD frame shall accept two recessive bits as ACK.
If receiver of CAN FD frame detect CRC error it shall signal it at first bit of EOF.
This means that during waiting it accepts CRC Delim + 2 ACK bits + ACK delim. Therefore
it shall start transmission of error frame 4 bits after the end of CRC field.
Currently CTU CAN FD start transmission of Error flag after 3 bits only!
This is bug and it shall be fixed.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/379Classical CAN version2021-05-28T19:43:16ZIlle, Ondrej, Ing.Classical CAN versionWhen PEX = 0 and FD Enabled = 0 bits are configured, device shall be conformant to "Classical CAN" config.
This is not true at the momemnt. In this config, recessive FDF bit causes form error (instead in Classical
CAN Config, it shall be...When PEX = 0 and FD Enabled = 0 bits are configured, device shall be conformant to "Classical CAN" config.
This is not true at the momemnt. In this config, recessive FDF bit causes form error (instead in Classical
CAN Config, it shall be accepted as recessive, but frame shall be still considered as CAN 2.0 received frame!)
Also, other reserved bits shall be accepted even if they are recessive!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/380PSL problems in TXT Buffer2020-10-27T20:05:31ZIlle, Ondrej, Ing.PSL problems in TXT BufferResolve problems with PSL expression in TXT Buffer FSM. Probably dont use
string concatenation within PSL report!Resolve problems with PSL expression in TXT Buffer FSM. Probably dont use
string concatenation within PSL report!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/381dff entity name seems to conflict with Quartus Prime reserved primitve name2020-10-17T12:03:21ZPavel Pisadff entity name seems to conflict with Quartus Prime reserved primitve nameThe synthesis for PCIe board and Intel SoC run by Quartus reports next problem
Warning (12018): Entity "dff" will be ignored because it conflicts with Quartus Prime primitive name File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/mod
...The synthesis for PCIe board and Intel SoC run by Quartus reports next problem
Warning (12018): Entity "dff" will be ignored because it conflicts with Quartus Prime primitive name File: /home/pi/fpga/altera/db4cgx15/pcie-ctu_can_fd/mod
ules/ctu_can_fd/src/common/dff.vhd Line: 50
I am not sure by what kind of component/entity is instance replaced. May it be that it is totally harmless warning but I would vote for rename anyway.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/382Update readme to mention QEMU emulation and Intel DE0-Nano-SoC support2020-10-21T23:27:05ZPavel PisaUpdate readme to mention QEMU emulation and Intel DE0-Nano-SoC supporthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/383doc: coorect QEMU doc/can.txt url.2020-10-21T23:31:54ZPavel Pisadoc: coorect QEMU doc/can.txt url.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/384Error counter reset after protocol exception2020-10-22T20:59:20ZIlle, Ondrej, Ing.Error counter reset after protocol exceptionWhen IUT detects protocol exception, it shall enter integration, but
it shall keep REC/TEC values unchanged.
Right now, upon leaving integration, error counters are reset. This needs
to be done only after device is started (when still i...When IUT detects protocol exception, it shall enter integration, but
it shall keep REC/TEC values unchanged.
Right now, upon leaving integration, error counters are reset. This needs
to be done only after device is started (when still in bus-off)ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/385specification: inconsisten names for timestamp in the frame buffer2020-10-28T16:40:04ZPavel Pisaspecification: inconsisten names for timestamp in the frame bufferTIMESTAMP_L_W has field TIME_STAMP_31_0
TIMESTAMP_U_W has field TIMESTAMP_L_W
Why? I was drenched in shame when I have read "This is crazy" in review referencing to automatically generated structures. Yes, it is possible to argue that ...TIMESTAMP_L_W has field TIME_STAMP_31_0
TIMESTAMP_U_W has field TIMESTAMP_L_W
Why? I was drenched in shame when I have read "This is crazy" in review referencing to automatically generated structures. Yes, it is possible to argue that the tool generates consistent constructs for all registers even that it has not significant meaning when it is full 32-single value one. But when you have no explanation for mismatch of names of the fields then it is a worse.
Please, consider what can be done with this. It can be marked as issue WontFix for 2.0 version, but should stay open and considered for some resolution.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/386driver: updates based on v6 patches review2020-10-26T11:34:23ZPavel Pisadriver: updates based on v6 patches reviewhttps://lkml.org/lkml/2020/10/22/249https://lkml.org/lkml/2020/10/22/249https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/387AHB test2023-12-17T20:38:17ZIlle, Ondrej, Ing.AHB testAt the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)At the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/388No synchronisation for transmitter during data bit-rate2020-10-29T20:15:41ZIlle, Ondrej, Ing.No synchronisation for transmitter during data bit-rateCurrently, transmitter does not synchronize during data bit rate
only if there is SSP. If SSP is not used during data bit rate by
transmitter, it still re-synchronizes, which is wrong!Currently, transmitter does not synchronize during data bit rate
only if there is SSP. If SSP is not used during data bit rate by
transmitter, it still re-synchronizes, which is wrong!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/389Datasheet clean-up vol. 22020-10-31T22:14:25ZIlle, Ondrej, Ing.Datasheet clean-up vol. 2Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to dis...Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to distuiguish betwen Base and Extended frames)
4. Add RTR suppression for frame filters.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/390Extend reintegration2020-11-05T20:02:20ZIlle, Ondrej, Ing.Extend reintegrationReintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive...Reintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive bits earlier than the tester (remember its all recessive bits,
so no resynchronization) and retransmitt earlier.
Good approach how to avoid this, is to demand 129 consecutive recessive repetitions
of 11 consecutive recessive bits.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/391Fix hard synchronization upon SOF start2020-11-21T16:52:24ZIlle, Ondrej, Ing.Fix hard synchronization upon SOF startIf dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC ...If dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC FSM is already in s_pc_sof. This means that it reacts to resynchronisation.
This can be fixed that hard sync will be valid also during SOF, but this approach must
be analyzed first.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/392Regression improvements2020-11-29T22:24:37ZIlle, Ondrej, Ing.Regression improvementsAdd test-cases to cover corner-cases of PSL coverage in TX Arbitrator.Add test-cases to cover corner-cases of PSL coverage in TX Arbitrator.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/393Functional coverage fix2020-12-09T21:17:47ZIlle, Ondrej, Ing.Functional coverage fixTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/394RX Buffer status extension2020-12-12T20:53:53ZIlle, Ondrej, Ing.RX Buffer status extensionImplement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] I...Implement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] Implement in RTL
3. [ ] Document
4. [ ] Write testISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/395Generic number of TXT Buffers2021-02-24T01:34:17ZIlle, Ondrej, Ing.Generic number of TXT BuffersThis task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implemen...This task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implement the change in RTL.
4. [x] Extend feature tests to check all buffers (in feature TB config use 8 TXT Buffers).https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/396Use kernel compliant register map in linux driver2021-09-25T09:46:44ZIlle, Ondrej, Ing.Use kernel compliant register map in linux driverLinux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/397Scan mode support on RTL.2021-05-05T14:45:33ZIlle, Ondrej, Ing.Scan mode support on RTL.Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/398Memory testability on RTL2021-05-02T17:47:16ZIlle, Ondrej, Ing.Memory testability on RTLImplement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these ...Implement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these registers.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/399Release package finalization2021-05-24T17:27:19ZIlle, Ondrej, Ing.Release package finalizationFrom artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component d...From artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component documentation.
4. [x] Result of latest regression, compliance regression, functional coverage.
5. [x] Xilinx and Altera FPGA components.
6. [x] Synthesis benchmark.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/400Datasheet and System Architecture clean-up2020-12-30T10:40:15ZIlle, Ondrej, Ing.Datasheet and System Architecture clean-up