CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-05-08T17:41:06Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/412Fix VRM generation for ASIC/FPGA fast test run2021-05-08T17:41:06ZIlle, Ondrej, Ing.Fix VRM generation for ASIC/FPGA fast test runhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/411Fix absolute links in TB documentation2021-05-07T14:20:01ZIlle, Ondrej, Ing.Fix absolute links in TB documentationhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/410Multiple compliance configs2021-05-16T14:18:17ZIlle, Ondrej, Ing.Multiple compliance configsCurrently, we run only single compliance test run. The aim of this issue is to extend this to
3 compliance test runss:
- minimal
- maximal
- typical
Each covering corner-case of bit-rate. It is question whether Miminal bit-rate is feasi...Currently, we run only single compliance test run. The aim of this issue is to extend this to
3 compliance test runss:
- minimal
- maximal
- typical
Each covering corner-case of bit-rate. It is question whether Miminal bit-rate is feasible,
since it would probably take too much time... Then choosing realistic "minimal" is needed.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/409core version 2.3 does not match value checked by regtest2021-03-04T20:51:20ZPavel Pisacore version 2.3 does not match value checked by regtesthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/408Optimize pages2021-02-27T13:06:09ZIlle, Ondrej, Ing.Optimize pagesRemove un-needed files from pages, since it is too large to be published.Remove un-needed files from pages, since it is too large to be published.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/406Functional coverage - cross check2021-05-17T11:42:22ZIlle, Ondrej, Ing.Functional coverage - cross checkFunctional coverage has several holes:
- Uncovered items -> Check if they can be covered and how
- Some blocks (TX_arbitrator.fsm), show less cover points in HTML report than there actually are in source code!Functional coverage has several holes:
- Uncovered items -> Check if they can be covered and how
- Some blocks (TX_arbitrator.fsm), show less cover points in HTML report than there actually are in source code!https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/405SETTINGS[TBFBO] feature test2021-02-20T08:14:07ZIlle, Ondrej, Ing.SETTINGS[TBFBO] feature testCurrently dedicated test is missing for TBFBO bit.Currently dedicated test is missing for TBFBO bit.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/402License update2021-02-04T20:27:46ZIlle, Ondrej, Ing.License updatehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/401Add repository clean script2021-01-10T20:26:03ZIlle, Ondrej, Ing.Add repository clean scriptAdd REST API script to clean pipeline data.Add REST API script to clean pipeline data.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/400Datasheet and System Architecture clean-up2020-12-30T10:40:15ZIlle, Ondrej, Ing.Datasheet and System Architecture clean-uphttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/399Release package finalization2021-05-24T17:27:19ZIlle, Ondrej, Ing.Release package finalizationFrom artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component d...From artifacts, a release package shall be created with following:
1. [x] RTL + list file with all RTL files and resolved compile dependencies.
2. [x] TB + list file for TB.
3. [x] Build datasheet, system architecture and TB component documentation.
4. [x] Result of latest regression, compliance regression, functional coverage.
5. [x] Xilinx and Altera FPGA components.
6. [x] Synthesis benchmark.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/398Memory testability on RTL2021-05-02T17:47:16ZIlle, Ondrej, Ing.Memory testability on RTLImplement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these ...Implement read/write access to memory buffers from user registers. Read/Write access shall
be enabled only in test mode and via dedicated registers. Also, there shall be generic, which
will conditionally enable/disable presence of these registers.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/397Scan mode support on RTL.2021-05-05T14:45:33ZIlle, Ondrej, Ing.Scan mode support on RTL.Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..Provide scan mode on RTL. Scan mode shall be enabled by input signal.
When scan mode is enabled, all flops which contribute to reset of another flop shall be gated..https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/396Use kernel compliant register map in linux driver2021-09-25T09:46:44ZIlle, Ondrej, Ing.Use kernel compliant register map in linux driverLinux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driver shall be able to use also Linux kernel compliant format for description of register map.
This task deals with extending register map generator with such target and swapping header with bit fields
for kernel compliant headers.Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/395Generic number of TXT Buffers2021-02-24T01:34:17ZIlle, Ondrej, Ing.Generic number of TXT BuffersThis task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implemen...This task should extend CTU CAN FD with number of TXT Buffers given by top level generic.
1. [x] Add corresponding fields in register map.
2. [x] Extend documentation (Datasheet and system architecture). Modify pictures.
3. [x] Implement the change in RTL.
4. [x] Extend feature tests to check all buffers (in feature TB config use 8 TXT Buffers).https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/394RX Buffer status extension2020-12-12T20:53:53ZIlle, Ondrej, Ing.RX Buffer status extensionImplement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] I...Implement status bit which will be 1 when READ_DATA points to start of new frame in RX Buffer.
This allows to add recover if user gets lost in reading RX Buffer (without flushing the buffer).
1. [ ] Add feature in register map.
2. [ ] Implement in RTL
3. [ ] Document
4. [ ] Write testISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/393Functional coverage fix2020-12-09T21:17:47ZIlle, Ondrej, Ing.Functional coverage fixTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/392Regression improvements2020-11-29T22:24:37ZIlle, Ondrej, Ing.Regression improvementsAdd test-cases to cover corner-cases of PSL coverage in TX Arbitrator.Add test-cases to cover corner-cases of PSL coverage in TX Arbitrator.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/391Fix hard synchronization upon SOF start2020-11-21T16:52:24ZIlle, Ondrej, Ing.Fix hard synchronization upon SOF startIf dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC ...If dominant bit starts in bus idle after sample point of third bit of intermission
and DUT has pending transmission, DUT shall executed hard sync (because, from flow
of time on bus, it is still in third bit of intermission).
But DUT PC FSM is already in s_pc_sof. This means that it reacts to resynchronisation.
This can be fixed that hard sync will be valid also during SOF, but this approach must
be analyzed first.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/390Extend reintegration2020-11-05T20:02:20ZIlle, Ondrej, Ing.Extend reintegrationReintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive...Reintegration shall last at least 128*11 recessive bits.
If reintegration counter is configured only to 128, this condition is satisfied.
But in reality, if device oscillator is off, then it might actually calculate
128 * 11 consecutive bits earlier than the tester (remember its all recessive bits,
so no resynchronization) and retransmitt earlier.
Good approach how to avoid this, is to demand 129 consecutive recessive repetitions
of 11 consecutive recessive bits.ISO optimizations