CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-09-25T07:53:30Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/438driver: update register maps for kernle driver build to match latest CTU CAN ...2021-09-25T07:53:30ZPavel Pisadriver: update register maps for kernle driver build to match latest CTU CAN FD version.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/434Re-work operating modes2023-12-17T20:25:10ZIlle, Ondrej, Ing.Re-work operating modesCurrently, there is only single bit which enables operation of CTU CAN FD (SETTINGS[ENA]).
All modes (ROM, LOM, STM, etc...) are handled by dedicated bits in MODE register, and the
protection of these bits is added to disallow their chan...Currently, there is only single bit which enables operation of CTU CAN FD (SETTINGS[ENA]).
All modes (ROM, LOM, STM, etc...) are handled by dedicated bits in MODE register, and the
protection of these bits is added to disallow their change during run-time.
It would be better, to have operating mode FSM, which would be communicating with protocol
control FSM, and have this FSM-state (device operating mode) exposed to user.
Right now it is unclear what is the behavior if multiple special modes are combined together.
It still needs to be re-though what will be the granularity of operating modes of the device.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/433Test linux kernel compliant driver on setup know to build.2021-09-25T00:57:15ZPavel PisaTest linux kernel compliant driver on setup know to build.There has been more changes in the core reported version and component Vivado component version etc. Test of the updated driver on some version know to work is a must to move forward.There has been more changes in the core reported version and component Vivado component version etc. Test of the updated driver on some version know to work is a must to move forward.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/432Delivery package fixes2021-09-19T14:54:51ZIlle, Ondrej, Ing.Delivery package fixesThere are several issues in the delivery package:
1. [x] List files contain source lists with the sub-directory, while "rtl" and "tb" folder contain flat list of files.
2. [x] Delivery package does not contain list of tests available wi...There are several issues in the delivery package:
1. [x] List files contain source lists with the sub-directory, while "rtl" and "tb" folder contain flat list of files.
2. [x] Delivery package does not contain list of tests available within the TB.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/431Debug stuck gate regression in CI2021-10-23T12:58:52ZIlle, Ondrej, Ing.Debug stuck gate regression in CICurrently one step of gate level simulations gets "stuck" and job fails on time-out. Figure out why.Currently one step of gate level simulations gets "stuck" and job fails on time-out. Figure out why.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/430Debug failing Compliance tests2023-12-15T13:40:03ZIlle, Ondrej, Ing.Debug failing Compliance testsThe aim of this issue is to debug last model mismatches compared to ISO compliance tests.
This will need modifications of ISO compliance model and test-sequence.The aim of this issue is to debug last model mismatches compared to ISO compliance tests.
This will need modifications of ISO compliance model and test-sequence.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/429Move to Release 2.42021-08-28T21:15:40ZIlle, Ondrej, Ing.Move to Release 2.4https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/428Modelsim cannot run simulation2021-08-26T17:07:32ZJan SobotkaModelsim cannot run simulationModelsim cannot run simulation due to scrict runtime bounds check. Modelsim version: ModelSim Intel FPGA Starter Edition 2020.1
```
# ** Fatal: (vsim-3709) Signal formal "ID_dec" bounds 0 to 2147483647 are not identical to actual bounds...Modelsim cannot run simulation due to scrict runtime bounds check. Modelsim version: ModelSim Intel FPGA Starter Edition 2020.1
```
# ** Fatal: (vsim-3709) Signal formal "ID_dec" bounds 0 to 2147483647 are not identical to actual bounds 0 to 536870911.
# Time: 0 ps Iteration: 0 Process: /can_fd_pcie_tb/dut_comp/CAN_FD_2_comp/frame_filters_inst/range_filter_inst/line__135 File: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/frame_filters/range_filter.vhd
# Fatal error in Architecture rtl at ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/frame_filters/range_filter.vhd line 135
```https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/427Change functional coverage coloring2021-08-27T07:44:45ZIlle, Ondrej, Ing.Change functional coverage coloringAdd dark green color for 100% covered blocks in functional coverage report.Add dark green color for 100% covered blocks in functional coverage report.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/426Modelsim don't ignore PSL assertions in VHDL code2021-08-19T13:33:54ZJan SobotkaModelsim don't ignore PSL assertions in VHDL codeI tried to compile core in ModelSim - INTEL FPGA STARER EDITION 2020.1 and it seems that PSL assertions are not ignored.
** Error: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/can_top_level.vhd(1035): syntax error, unexpected "IDEN...I tried to compile core in ModelSim - INTEL FPGA STARER EDITION 2020.1 and it seems that PSL assertions are not ignored.
** Error: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/can_top_level.vhd(1035): syntax error, unexpected "IDENTIFIER", expecting ';'
** Error: ~/CAN_Test/FPGA_design/lib/ctu_canfd_ip_core/src/can_top_level.vhd(1046): near "txtb_asr_gen": An embedded PSL statement may not be separated by a non-comment statement.
![vsim_error](/uploads/f25dc16b6cf1114682ab90cb0a2152e3/vsim_error.PNG)
Another affected files:\
Compile of can_top_level.vhd failed with 2 errors.\
Compile of txt_buffer_fsm.vhd failed with 1 errors.\
Compile of tx_arbitrator.vhd failed with 2 errors.\
Compile of rx_buffer_fsm.vhd failed with 1 errors.\
Compile of rx_buffer.vhd failed with 4 errors.\
Compile of trigger_generator.vhd failed with 2 errors.\
Compile of rx_shift_reg.vhd failed with 1 errors.\
Compile of protocol_control_fsm.vhd failed with 1 errors.\
Compile of protocol_control.vhd failed with 2 errors.\
Compile of operation_control.vhd failed with 2 errors.\
Compile of err_counters.vhd failed with 2 errors.\
Compile of crc_calc.vhd failed with 2 errors.\
Compile of can_core.vhd failed with 2 errors.\
Compile of bus_traffic_counters.vhd failed with 2 errors.\
Compile of bit_destuffing.vhd failed with 2 errors.\
Compile of tx_data_cache.vhd failed with 2 errors.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/425Fix documentation headers2021-07-03T12:22:21ZIlle, Ondrej, Ing.Fix documentation headershttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/424Time triggered transmission mode2021-06-18T21:57:55ZIlle, Ondrej, Ing.Time triggered transmission modeAt the moment, frame is only transmitted when external timestamp is higher than timestamp
in TXT Buffer. If frame shall be transmitted immediately, then user shall write 0x0 to
both timestamp words. If timestamp is not used, then it shal...At the moment, frame is only transmitted when external timestamp is higher than timestamp
in TXT Buffer. If frame shall be transmitted immediately, then user shall write 0x0 to
both timestamp words. If timestamp is not used, then it shall be tied high in design which
integrates CTU CAN FD.
It would be better if Time triggered transmission would be enabled/disabled by a dedicated mode,
and it would be disabled by default. This will avoid confusion and errors in following case:
timestamp input is not tied high, but low instead (by mistake). If user inserts non-zero
value to timestamp words in TXT buffer -> Frame will never be transmitted. If time triggered
transmission is disabled by default, user will not see this issue. Also, since user knows
that Timestamp is not available, he will most likely not try to enable this mode.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/423Pipeline fixes2021-06-17T18:19:39ZIlle, Ondrej, Ing.Pipeline fixeshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/422RX Buffer manual read2021-06-14T20:02:22ZIlle, Ondrej, Ing.RX Buffer manual readIntroduce additional mode which allows reading from RX buffer via 4x8 bit reads,
or 2x16 bit reads. This mode could be switched in MODE register. If this mode is
active, then read from RX_DATA register will not have side-effect of moving...Introduce additional mode which allows reading from RX buffer via 4x8 bit reads,
or 2x16 bit reads. This mode could be switched in MODE register. If this mode is
active, then read from RX_DATA register will not have side-effect of moving
read pointer to next position. Moving of read pointer to next position will be then
realized by writing a bit to CMD register.
This is an alternative to caching solution if CTU CAN FD is to be integrated into
8/16bit systems.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/420RTL: Use entity binding indication instead of component2021-06-04T10:52:43ZIlle, Ondrej, Ing.RTL: Use entity binding indication instead of componenthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/419Coverage clean-up2021-06-03T12:54:03ZIlle, Ondrej, Ing.Coverage clean-upAims to clean code+functional coverage before release 3.0Aims to clean code+functional coverage before release 3.0https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/418Convert logs into more user-friendly format2021-05-23T18:56:43ZIlle, Ondrej, Ing.Convert logs into more user-friendly formatCurrently, Vunit exports JUnit style report. It would be good if this can be converted
either into plain HTML or other format which is easier to view. Chrome by default
does not allow opening XML files (due to security concerns).
Hopefu...Currently, Vunit exports JUnit style report. It would be good if this can be converted
either into plain HTML or other format which is easier to view. Chrome by default
does not allow opening XML files (due to security concerns).
Hopefully, this is not too much size. At the moment. XMLs are compressed in pages.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/417Vivado component updates2021-06-02T19:33:59ZIlle, Ondrej, Ing.Vivado component updatesCurrently, Vivado component is out-dated, it does not contain newest generics nor ports.
This issue shall update the Vivado component as well as adding it to exported package in "pages".Currently, Vivado component is out-dated, it does not contain newest generics nor ports.
This issue shall update the Vivado component as well as adding it to exported package in "pages".https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/415Gate level simulation2021-05-23T12:07:02ZIlle, Ondrej, Ing.Gate level simulationCurrently, GHDL does not support Verilog, nor does Vivado support exporting
VHDL timing netlist with VITL. Therefore timing gate level simulation
is not really possible...
However, Vivado should support VHDL models of FPGA cells via "uni...Currently, GHDL does not support Verilog, nor does Vivado support exporting
VHDL timing netlist with VITL. Therefore timing gate level simulation
is not really possible...
However, Vivado should support VHDL models of FPGA cells via "unisim" library.
This should be unit delay simulation.
Following approach might be good:
1. Run Synthesis during "build" phase. Will be done in #212 .
2. Export netlist in VHDL/EDIF format to "test" phase.
3. Have one test configuration (mix of feature, compliance runs), which will
run tests on gates.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/413Fault tolerance optimizations2022-07-18T08:53:01ZIlle, Ondrej, Ing.Fault tolerance optimizationsImplement Fault tolerance in CTU CAN FDs design:
1. [x] Implement ECC protection on TXT and RX Buffers.
2. [x] Implement Backup TXT Buffer mode.
Verification of ECC mechanism would require GHDL to have external names working
to force v...Implement Fault tolerance in CTU CAN FDs design:
1. [x] Implement ECC protection on TXT and RX Buffers.
2. [x] Implement Backup TXT Buffer mode.
Verification of ECC mechanism would require GHDL to have external names working
to force value in the middle of design and verify that Error is truly detected !
This option could be present as synthesis option ("sup_fault_tolerance").
It is questionable how to implement ECC protection, adding a single bit per memory
word could be held in array of flops.