CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2018-06-06T13:04:20Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/125Consolidate test library2018-06-06T13:04:20ZIlle, Ondrej, Ing.Consolidate test libraryThis issue should cover following topics:
1. Consolidation of CANtestlib.vhd. Add missing comments, format the code properly (4 spaces indent), remove unnecessary
functions
2. Add new set of functions which can be used in "feature t...This issue should cover following topics:
1. Consolidation of CANtestlib.vhd. Add missing comments, format the code properly (4 spaces indent), remove unnecessary
functions
2. Add new set of functions which can be used in "feature test". Due to many changes in the register map, most of the
feature tests are broken. If feature tests will be repaired, and register map changes again, there will be need for
further reparations! This is undesirable. There is an idea to create set of low level functions which access
the registers (sth. like HAL) and feature tests will only use these functions to execute tests. If register map changes,
only test library must be updated, and test code and test logic can remain unchanged!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/81sanity test: distribution of gap between two noise pulses2018-06-06T13:04:20ZMartin Jeřábeksanity test: distribution of gap between two noise pulsesGap between two noise pulses is an interval and IMO follows exponential distribution, not normal. For more exact simulation, this can be reflected (but it's a detail).
On another note, we may use the PRNG implemented in ieee.math_real (...Gap between two noise pulses is an interval and IMO follows exponential distribution, not normal. For more exact simulation, this can be reflected (but it's a detail).
On another note, we may use the PRNG implemented in ieee.math_real (uniform) and then transform it to the desired distribution. On the plus side, we will be able to change the seed. It is a question, however, how the performance will be affected.
Normal: N(m,v) = sqrt(-2.0 * log(u1)) * cos(2*pi*u2) * var + mean [Box-Muller]
Exponential: E(1/beta) = -log(u)*beta
(u from U(0,1))Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/118Fault confinement unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Fault confinement unit testImplement missing unit test for fault confinement circuit.Implement missing unit test for fault confinement circuit.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/137Remove simulation warnings2018-06-06T13:04:20ZIlle, Ondrej, Ing.Remove simulation warningsSimulation warnings are caused by un-initialized values of signals. Remove them, either initialize
signal values, or find simulation setting which will remove the warnings.Simulation warnings are caused by un-initialized values of signals. Remove them, either initialize
signal values, or find simulation setting which will remove the warnings.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/132interrupt enable/mask/status2018-06-06T13:04:20ZMartin Jeřábekinterrupt enable/mask/statusAt the moment interrupts work as following:
- INT_STAT_RAW: raw intrerupt status, independent of enable/mask (not exposed at the moment)
- INT_STAT = INT_STAT_RAW & INT_ENA (acc to datasheet should be INT_MASK instead)
- irq generated if...At the moment interrupts work as following:
- INT_STAT_RAW: raw intrerupt status, independent of enable/mask (not exposed at the moment)
- INT_STAT = INT_STAT_RAW & INT_ENA (acc to datasheet should be INT_MASK instead)
- irq generated if INT_STAT_RAW & INT_ENA & INT_MASK
Issue 1:
Swapped INT_ENA, INT_MASK.
Issue 2:
The mask sense is reversed. Usually when an interrupt bit is masked, it means that it does *not* cause irq generation.
Issue 3:
The value of INT_MASK is questionable. Basically we have 2 settings doing the same thing (enabling IRQ generation), which is useless (correct me if I am wrong). I would also like more if INT_STAT was completely unmasked, i.e. equal to INT_STAT_RAW.
If the masked variant should be desired, it should be masked solely by INT_ENA and INT_MASK would be removed.
It remains to be decided whether we should have (INT_STAT, INT_STAT_MASKED) or (INT_STAT_RAW, INT_STAT), that is if we keep the masked variant at all.
It could make sense to mask irq generation from particular TX buffers - then the TXBHCI bit would not be set if the particular buffer irqs were masked. Here the unmasked _RAW variant of the status register would not make sense.
However, I do not see much value in this for now, so I would just propose the following:
- remove INT_MASK
- do not mask INT_STATUSBug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/126Extend bit stuffing unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Extend bit stuffing unit testAt the moment Bit Stuffing unit test is missing SW modeled behaviour (of either Bit Stuffing or Bit destuffing)
which would calculate bit stuffing in behavioral way.
Add such a model and verify that bit stuffing is always returning the ...At the moment Bit Stuffing unit test is missing SW modeled behaviour (of either Bit Stuffing or Bit destuffing)
which would calculate bit stuffing in behavioral way.
Add such a model and verify that bit stuffing is always returning the same results as this model.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/130TX Arbitrator pipeline + Hazard unit2018-06-06T13:04:20ZIlle, Ondrej, Ing.TX Arbitrator pipeline + Hazard unitThe latest (End of April 2018) synthesis results in Xilinx and Altera Technologies are limited by (not surprisingly) the same combinational paths. The maximum frequencies are somewhere around 90 - 95 MHz. It would be nice to move to 100 ...The latest (End of April 2018) synthesis results in Xilinx and Altera Technologies are limited by (not surprisingly) the same combinational paths. The maximum frequencies are somewhere around 90 - 95 MHz. It would be nice to move to 100 and above.
The reason for this is following:
1. HW and SW commands are applied simultaneously and are completely asynchronous (not in the clock domain sense, rather in "both can happend at any time without knowing about each other").
2. Due to 1. , SW Commands, HW commands and TXT Buffer priorities and "ready indication" are evaluated combinationally!
Such an evaluation contains following combinational paths:
A) Starts in SW command register and TXT Buffer priorities.
B) Propagates through "priority decoder to "select_buf_index" and "select_buf_avail".
C) These values are used to control flow of TX Arbitrator FSM (e.g. restarting on change of "select_buf_index").
D) TX Arbitrator FSM is loading metadata and timestamp from TXT Buffers. Since It takes one clock cycle for RAM,
propagate data to the output, metadata_pointer in TX Arbitrator must be decoded combinationally! The same condition
which causes TX Arbitrator FSM state transition, must be used to combinationally address word in TXT_Buffer memory
in TXT Buffer word (address) which is needed by successive state of FSM.
E) Due to combinational driver on "metadata_pointer", pointer to TXT RAM is not registered and causes path from A up to
hard-core address decoder in RAM.
3. Combinational paths from 2. cause problems in both Technologies (according to Martin Jerabek in Xilinx SoC, there is RAM problem), and in Altera Cyclone V, first 1000 worst paths (about first 2 ns slack) are caused by these paths.
To bring CTU CAN FD Core this problem must be resolved.
Following solutions are available:
1. Implement pipeline between priority decoder and TX Arbitrator FSM. This would however require additional synchronisation
of HW and SW command in new unit "e.g. Hazard unit to have cool naming..."
2. Simpler solution would be to add new state to TX Arbitrator state machine, which would ALWAYS address metadata pointer
with registered value! This would add next clock cycle to data loading (extend to 4 from 3 clock cycles), however it is
easier solution than Hazard unit. One thing would still remain problematic. Address pointer would need to be set two
clock cycles (two states) before data from its address are needed. This would be a problem in state where state
transition is evaluated based on condition. Such a condition might have different value one clock cycle before,
than during the cycle that causes the transition!Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/37Protocol control unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Protocol control unit testUpdate Protocol Control unit test to be compatible with serialized data interface to TXT buffer and to RX Buffer.
Make sure that unit test properly covers the CRC calculation of ISO and non-ISO CAN FD.Update Protocol Control unit test to be compatible with serialized data interface to TXT buffer and to RX Buffer.
Make sure that unit test properly covers the CRC calculation of ISO and non-ISO CAN FD.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/13Prescaler unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Prescaler unit testExtend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Extend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/144Event logger unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Event logger unit testFinish event logger unit test. Make sure that it covers expected functionality of
event logger. Debug event logger module if necessary.Finish event logger unit test. Make sure that it covers expected functionality of
event logger. Debug event logger module if necessary.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/152ipyxact_parser is checked in as a submodule, but not declared in .gitmodules2018-06-06T12:54:12ZMartin Jeřábekipyxact_parser is checked in as a submodule, but not declared in .gitmodulesAdd as a submodule. Now recursive clone fails.
```
fatal: No url found for submodule path 'modules/CTU_CAN_FD/scripts/pyXact_generator/ipyxact_parser' in .gitmodules
```Add as a submodule. Now recursive clone fails.
```
fatal: No url found for submodule path 'modules/CTU_CAN_FD/scripts/pyXact_generator/ipyxact_parser' in .gitmodules
```Bug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/151Fix ALC2018-06-06T11:31:00ZIlle, Ondrej, Ing.Fix ALCRe-enable Arbitration lost capture functionality.
Modify IP-XACT documentation.Re-enable Arbitration lost capture functionality.
Modify IP-XACT documentation.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/99Event logger BRS bugfix2018-06-05T17:07:28ZIlle, Ondrej, Ing.Event logger BRS bugfixFix temporary logging of BRS event which is always logging bit-rate shift from NOMINAL to DATA.Fix temporary logging of BRS event which is always logging bit-rate shift from NOMINAL to DATA.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/112TX Arbitrator unit test2018-06-02T22:02:51ZIlle, Ondrej, Ing.TX Arbitrator unit testTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/117Remove obsolete config options2018-06-02T21:36:37ZIlle, Ondrej, Ing.Remove obsolete config optionsSince major savings in LUT consumption were achieved, following settings of the Core now become osbolete:
support_be
tx_time_sup
Remove these two options.Since major savings in LUT consumption were achieved, following settings of the Core now become osbolete:
support_be
tx_time_sup
Remove these two options.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/115Hard sync in the EDL2018-05-31T17:27:44ZIlle, Ondrej, Ing.Hard sync in the EDLAccording to CAN FD specification Hard synchronisation should be performed in the EDL bit of CAN FD Frame.
In the actual implementation this Hard synchronisation is omitted since Prescaler did not support
Hard synchronisation in the midd...According to CAN FD specification Hard synchronisation should be performed in the EDL bit of CAN FD Frame.
In the actual implementation this Hard synchronisation is omitted since Prescaler did not support
Hard synchronisation in the middle of CAN Frame. In extreme cases (e.g. setting nominal SJW to 0) this could
cause improper operation and inability to receive CAN FD frames.
The aim of this task is to add Hard-synchronisation in the EDL bit of CAN FD Frame.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/139CI: HTTPS and token passing for Flask proxy2018-05-25T12:14:37ZMartin JeřábekCI: HTTPS and token passing for Flask proxy- set up certbot+cron on hathi
- set up nginx in docker, link the certs via volume
- put the pipeline trigger token as a secret token for the webhook
- modify the app to take the token from the header- set up certbot+cron on hathi
- set up nginx in docker, link the certs via volume
- put the pipeline trigger token as a secret token for the webhook
- modify the app to take the token from the headerContinuous integrationMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/136APB wrapper test2018-05-25T09:48:51ZMartin JeřábekAPB wrapper testEssentially identical to #71, but APB is much simpler than AXI.
Should probably be a unit test, testing the following:
- read from a register
- write to a register, reading back the same value
- write with byte enable
- access to the...Essentially identical to #71, but APB is much simpler than AXI.
Should probably be a unit test, testing the following:
- read from a register
- write to a register, reading back the same value
- write with byte enable
- access to the register with the highest address to verify correct address passing
- read just after (or during) HW reset correctly stalls until the core is readyTest maintenanceMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/142Sanity test failing to compile2018-05-25T09:48:51ZMartin JeřábekSanity test failing to compileError introduced in 9b09dea6b629a4a083286f5.Error introduced in 9b09dea6b629a4a083286f5.Martin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/122Set up gitlab continuous integration (CI)2018-05-24T19:23:23ZMartin JeřábekSet up gitlab continuous integration (CI)Set up basic CI/CD to run short sanity test after each commit. For now, use the available shared runner.Set up basic CI/CD to run short sanity test after each commit. For now, use the available shared runner.Continuous integrationMartin JeřábekMartin Jeřábek