CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2019-01-20T16:36:10Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/213Timestamp register feature test2019-01-20T16:36:10ZIlle, Ondrej, Ing.Timestamp register feature testAdd small feature test reading from TIMESTAMP registers which will store value of an external timestamp,
read value from these registers (several times), and check that timestamp is matching the value read
from the registers.
Feature of...Add small feature test reading from TIMESTAMP registers which will store value of an external timestamp,
read value from these registers (several times), and check that timestamp is matching the value read
from the registers.
Feature of reading the value of timestamp from register first must be implemented in:
https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core/issues/208Test improvementsIng. Viktor FúraIng. Viktor Fúrahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/212Automatization of resource benchmarks2021-05-24T14:16:21ZIlle, Ondrej, Ing.Automatization of resource benchmarksSince the outcome of synthesis is highly dependant on tool settings, FPGA family etc..., the best result
from area/performance point of view must be often hand-tuned.
Actually, there exists only Benchmark project and set of constraints f...Since the outcome of synthesis is highly dependant on tool settings, FPGA family etc..., the best result
from area/performance point of view must be often hand-tuned.
Actually, there exists only Benchmark project and set of constraints for evaluation. This is not enough.
This task aims at creating automatized FPGA synthesis scripts for both Xilinx and Intel Families.
General flow of automatic script should be like so:
1. Create project from sources. Avoid explicit reference, add all files in "src" folder.
2. Load constraints for Xilinx or Intel. Avoid explicit paths, preffer usage of "type" constraint.
3. Configure synthesis settings, preffer forbidding hierarchy flattening. Configure synthesis out of context.
4. Run synthesis and post-synthesis optimization.
5. Export Netlist in VHDL/Verilog/EDIF format.
6. Export "Design checkopoints" or "IP-Wrapper" or what the hell it is called on Intel devices...
7. Run timing analysis on post-synthesis netlist. Verify that it passed and there are no negative slacks.
8. Export Maximum operating frequency and number of used resources in the netlist.Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/211Add VHDL configurations2019-03-18T22:28:18ZIlle, Ondrej, Ing.Add VHDL configurationsAdd VHDL configuration for each file from "src".Add VHDL configuration for each file from "src".ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/210Prescaler FSM rework2019-03-19T22:41:07ZIlle, Ondrej, Ing.Prescaler FSM reworkSeparate Prescaler FSM into stand-alone module.
Avoid ugly logic for sync trigger generation in h_sync state.Separate Prescaler FSM into stand-alone module.
Avoid ugly logic for sync trigger generation in h_sync state.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/209Remove regmap gen files from project.2018-12-08T17:04:16ZIlle, Ondrej, Ing.Remove regmap gen files from project.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/208add registers for reading current timestamp2019-01-02T15:24:10ZMartin Jeřábekadd registers for reading current timestampStrictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and t...Strictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and the counter value is inaccessible there - at all. So it would be nice to have read-only access to it via the CAN core in case the integrator forgets to make it accessible from the counter directly again. As a bonus, it will be simpler to handle the timestamps in Linux driver, because it will not have to depend on an external timer.
Will be useful for #158.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/207Design decoupling2019-01-05T00:01:41ZIlle, Ondrej, Ing.Design decouplingThe aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x...The aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x] Move RX Buffer FSM to a separate entity
4. [x] Create generic instances of Range Filter and Bit Filter.
5. [x] Generic instance of Re-synchronizer in BusSync.
6. [x] Create generic Interrupt Module and instantiate array of these modules.
7. [x] Move all CRCs and CRC mux logic in CAN Core to separate wrapper!
8. [x] Re-factor Bit Stuffing
9. [x] Re-factor Bit De-stuffing
6. [x] Re-organize SRC folder structure.
7. [x] Accustomize wave files for newly introduced signals.
8. [x] Modify documentation (file names, accustomize pictures)
ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/206Create basic test library2019-01-19T23:18:00ZIlle, Ondrej, Ing.Create basic test libraryUse VUnit "log" and "check" library all over the testcases:
1. [x] Add includes for "log" and "check" library. Resolve all things that must be changed in run.py script.
2. [x] Change all TCs to use VUnit log function.
3. [x] Remove old ...Use VUnit "log" and "check" library all over the testcases:
1. [x] Add includes for "log" and "check" library. Resolve all things that must be changed in run.py script.
2. [x] Change all TCs to use VUnit log function.
3. [x] Remove old log function in CANTestlib and all related structs. Think about severities.
4. [x] Use Check library to replace explicit "if" comparisons.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/205SSP offset feature test2020-01-12T21:11:35ZIlle, Ondrej, Ing.SSP offset feature testImplement feature test for secondary sampling point user defined offset.
All options of SW offset, measured offset, SW + measured offset must be executed.Implement feature test for secondary sampling point user defined offset.
All options of SW offset, measured offset, SW + measured offset must be executed.Test improvementsIng. Viktor FúraIng. Viktor Fúrahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/204SSP offset2019-01-06T10:30:16ZIlle, Ondrej, Ing.SSP offsetImplement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for S...Implement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for SSP offset:
1. Use only measured value
2. Use only SW offset.
3. Use measured value + SW offset.
Addition of trv_delay and SW SSP offset will be realized inside Bus Sampling
module, since shift registers for secondary sampling are implemented there.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/203Protocol exception behaviour2019-08-04T11:40:32ZIlle, Ondrej, Ing.Protocol exception behaviourAdd Flag of Protocol exception behaviour as defined in ISO conformance test plan.
Protocol exception shall be like a flag and set when:
drv_fd_ena is set to 0 and r0 (EDL) bit of CAN 2.0 frame is received RECESSIVE.
drv_fd_ena is set to ...Add Flag of Protocol exception behaviour as defined in ISO conformance test plan.
Protocol exception shall be like a flag and set when:
drv_fd_ena is set to 0 and r0 (EDL) bit of CAN 2.0 frame is received RECESSIVE.
drv_fd_ena is set to 1 and r0 bit of CAN FD frame is received RECESSIVE.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/202TXT Buffer hazard test2019-01-23T21:04:19ZIlle, Ondrej, Ing.TXT Buffer hazard testImplement test-case which will verify that TX Buffer datapath is hazard free.
Such a test case should do following things in a loop (e.g 50 times in single iteration):
1. Insert frame to TXT Buffer
2. Mark the buffer as ready.
3. Immed...Implement test-case which will verify that TX Buffer datapath is hazard free.
Such a test case should do following things in a loop (e.g 50 times in single iteration):
1. Insert frame to TXT Buffer
2. Mark the buffer as ready.
3. Immediately send set_abort command.
4. Readout status of the buffer.
5. If the buffer is "aborted", check that no transmission is in progress (e.g. via STATUS), throw an error if not.
6. If the buffer is "abort in progress" check that transmission is in progress, and wait till its end. Throw an error if not.
7. If buffer is in any other state, throw an error.Test improvementsIng. Viktor FúraIng. Viktor Fúrahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/201RX Buffer functional coverage2019-02-08T15:17:15ZIlle, Ondrej, Ing.RX Buffer functional coverageImplement functional coverage for RX FIFO:
At least following cases should be covered:
1. [x] Buffer empty
2. [x] Buffer full
3. [x] Buffer overflow
4. [x] Buffer read-write at the same time
5. [x] Buffer read-write just after/before ea...Implement functional coverage for RX FIFO:
At least following cases should be covered:
1. [x] Buffer empty
2. [x] Buffer full
3. [x] Buffer overflow
4. [x] Buffer read-write at the same time
5. [x] Buffer read-write just after/before each other (one clock cycle)
6. [x] Data overrun occurs.
7. [x] Read by burst (memory pointer muxed).
8. [x] Storing SOF timestamp (in FSM).
9. [x] Storing EOF timestamp (in FSM).
10. [x] Storing RTR frame
11. [x] Storing Frame with 1, 2, 3 and 16 memory words for data.
12. [x] Stashing frame based on memory full.
13. [x] Stashing frame based on error frame (rec_abort).
14. [x] Buffer reset by SW.Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/200Bring-up GHDL functional coverage.2019-02-02T11:15:18ZIlle, Ondrej, Ing.Bring-up GHDL functional coverage.The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated ...The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated in a coverage output.
4. [x] Add PSL coverage gatherhing settings to config file
5. [x] Create PSL statement directly to directory with functional coverage without copyingFunctional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/199ISO testbench2023-12-15T13:39:29ZIlle, Ondrej, Ing.ISO testbenchCreate testbench for CAN ISO Conformance test plan with CAN Bit timing model and CAN Bit timing Library.Create testbench for CAN ISO Conformance test plan with CAN Bit timing model and CAN Bit timing Library.ISO conformance testinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/198CAN Bit timing model2020-12-06T18:14:13ZIlle, Ondrej, Ing.CAN Bit timing modelImplement CAN bit timing model which will be controlled by CAN Bit Timing library.Implement CAN bit timing model which will be controlled by CAN Bit Timing library.ISO conformance testinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/197ISO test library implementation2020-12-06T18:14:02ZIlle, Ondrej, Ing.ISO test library implementationImplement library as defined in ISO test framework spec.Implement library as defined in ISO test framework spec.ISO conformance testinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/196ISO test framework spec2020-12-06T18:13:52ZIlle, Ondrej, Ing.ISO test framework specCreate specification of:
1. CAN test framework library.
2. CAN bit timing model.
3. Commands applied from test-case on CAN Bit-timing library.Create specification of:
1. CAN test framework library.
2. CAN bit timing model.
3. Commands applied from test-case on CAN Bit-timing library.ISO conformance testinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/195TX Buffer explicit memory2018-10-31T20:22:24ZIlle, Ondrej, Ing.TX Buffer explicit memoryAs RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.As RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/194Protocol Control rework2019-08-02T16:42:29ZIlle, Ondrej, Ing.Protocol Control reworkRe-write Protocol control into separate FSMs to achieve higher modularity, cleaner design and possible lower ALM usage.Re-write Protocol control into separate FSMs to achieve higher modularity, cleaner design and possible lower ALM usage.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.