CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2019-01-10T19:02:58Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/241Align TIMESTAMP to 64 bit Address2019-01-10T19:02:58ZIlle, Ondrej, Ing.Align TIMESTAMP to 64 bit AddressMove TIMESTAMP_HIGH and TIMESTAMP_LOW registers to be aligned to 64 bit address.Move TIMESTAMP_HIGH and TIMESTAMP_LOW registers to be aligned to 64 bit address.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/240Driver sources formating.2019-01-10T18:49:28ZPavel PisaDriver sources formating.Run sources through `checkpatch.pl` Linux script. Script has to be invoked from Linux sources.
```
scripts/checkpatch.pl -f /home/pi/fpga/can-fd/ctu-can-fd/CAN_FD_IP_Core/driver/*.[ch]
```
Parameter `--fix-inplace` can be used to do som...Run sources through `checkpatch.pl` Linux script. Script has to be invoked from Linux sources.
```
scripts/checkpatch.pl -f /home/pi/fpga/can-fd/ctu-can-fd/CAN_FD_IP_Core/driver/*.[ch]
```
Parameter `--fix-inplace` can be used to do some basic cleanup of files.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/216Interfacing CAN FD core to PCI Express bus2019-01-10T17:47:17ZPavel PisaInterfacing CAN FD core to PCI Express busThe goal of the work is to interface [CTU CAN FD core](https://gitlab.fel.cvut.cz/canbus/CAN_FD_IP_Core) to [PCI Express](https://en.wikipedia.org/wiki/PCI_Express) bus which allows
its use on regular PC hardware.
The Devboards Gmb [DB4...The goal of the work is to interface [CTU CAN FD core](https://gitlab.fel.cvut.cz/canbus/CAN_FD_IP_Core) to [PCI Express](https://en.wikipedia.org/wiki/PCI_Express) bus which allows
its use on regular PC hardware.
The Devboards Gmb [DB4CGX15](https://www.devboards.de/en/home/products/product-details/article/db4cgx15/) board has been used for the work. The board is based on Intel/Altera EP4CGX15
Cyclone IV FPGA. Addon IO expander with CAN FD transceiver has been used. It has been initially
designed at PiKRON Ltd. for A0B36APO course [semestral work](https://cw.fel.cvut.cz/old/courses/a0b36apo/en/tutorials/10/start).
Unmodified CTU CAN FD core has been included in separated project [PCIe CTU CAN FD](https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd). Quartus QSYS is used to
map the core over Avalon to External Bus Bridge to IP_Compiler for PCI Express hard PCIe
core to PCIe bus.
The project contains design files, configuration files and scripts to test PCIe design
and to program device by Qurtus and indepedently by commandline [UrJTAG](http://urjtag.org/)
open-source tool.
PCIe support has been implemented for CTU CAN FD driver and result has been integrated to main
CTU CAN FD repository.Linux driverPavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/235Documentation - do not reference Avalon by mistake in APB decription2019-01-09T20:11:08ZPavel PisaDocumentation - do not reference Avalon by mistake in APB decription2.1.3 APB memory interface
Table 2.4 lists signals of CTU CAN FD on APB memory interface. When using CTU CAN FD with **Avalon Interface**,
can_top_apb from “src/can_top_apb.vhd” entity must be used. APB memory interface has no address c...2.1.3 APB memory interface
Table 2.4 lists signals of CTU CAN FD on APB memory interface. When using CTU CAN FD with **Avalon Interface**,
can_top_apb from “src/can_top_apb.vhd” entity must be used. APB memory interface has no address constraints ashttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/239Regmap gen saturation fix.2019-01-08T20:13:20ZIlle, Ondrej, Ing.Regmap gen saturation fix.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/238Accustomize reg.map gen2019-01-08T19:04:03ZIlle, Ondrej, Ing.Accustomize reg.map genAccustomize reg.map gen to not to need VHDL 2008.Accustomize reg.map gen to not to need VHDL 2008.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/237Update Quartus CTU CAN FD core benchmark project.2019-01-07T22:12:29ZPavel PisaUpdate Quartus CTU CAN FD core benchmark project.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/236vivado component: update to match bus_sampling changes.2019-01-07T12:18:17ZPavel Pisavivado component: update to match bus_sampling changes.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/226VHDL 2008 is not supported in Vivado IP packager still2019-01-07T09:23:57ZPavel PisaVHDL 2008 is not supported in Vivado IP packager stillhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/231Reset of memory registers2019-01-06T16:36:08ZIlle, Ondrej, Ing.Reset of memory registersRe-work of registers with register map generator brought another bug.
Register modules are not anymore reset by MODE[RST], they are reset only by "res_n" input.Re-work of registers with register map generator brought another bug.
Register modules are not anymore reset by MODE[RST], they are reset only by "res_n" input.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/219Create wave file for registers2019-01-06T16:02:56ZIlle, Ondrej, Ing.Create wave file for registersAdd new wave file with all register values as they are implemented after automatic generation of register map.Add new wave file with all register values as they are implemented after automatic generation of register map.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/227Documentation clarification - register modifications.2019-01-06T12:49:26ZIlle, Ondrej, Ing.Documentation clarification - register modifications.Explicitly clarify which register can be written only when core is disabled (SETTINGS[ENA]=0).
Out of top of my head for sure BTR, BTR_FD registers.
@jerabma7 @pisa @jnovak What do you think, which others?Explicitly clarify which register can be written only when core is disabled (SETTINGS[ENA]=0).
Out of top of my head for sure BTR, BTR_FD registers.
@jerabma7 @pisa @jnovak What do you think, which others?ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/228MODE.RST bit does not autoclear as it should. Driver is not functional withou...2019-01-06T10:55:28ZPavel PisaMODE.RST bit does not autoclear as it should. Driver is not functional without it.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/204SSP offset2019-01-06T10:30:16ZIlle, Ondrej, Ing.SSP offsetImplement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for S...Implement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for SSP offset:
1. Use only measured value
2. Use only SW offset.
3. Use measured value + SW offset.
Addition of trv_delay and SW SSP offset will be realized inside Bus Sampling
module, since shift registers for secondary sampling are implemented there.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/224Adapt canbench-sw and CTU_CAN_FD Vivado component to match sources after 207-...2019-01-05T18:59:01ZPavel PisaAdapt canbench-sw and CTU_CAN_FD Vivado component to match sources after 207-design-decoupling mergeFor now, assigned to me.For now, assigned to me.Pavel PisaPavel Pisahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/207Design decoupling2019-01-05T00:01:41ZIlle, Ondrej, Ing.Design decouplingThe aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x...The aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x] Move RX Buffer FSM to a separate entity
4. [x] Create generic instances of Range Filter and Bit Filter.
5. [x] Generic instance of Re-synchronizer in BusSync.
6. [x] Create generic Interrupt Module and instantiate array of these modules.
7. [x] Move all CRCs and CRC mux logic in CAN Core to separate wrapper!
8. [x] Re-factor Bit Stuffing
9. [x] Re-factor Bit De-stuffing
6. [x] Re-organize SRC folder structure.
7. [x] Accustomize wave files for newly introduced signals.
8. [x] Modify documentation (file names, accustomize pictures)
ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/183driver: stuck in interrupt on RX buffer overrun2019-01-02T17:33:21ZMartin Jeřábekdriver: stuck in interrupt on RX buffer overrunMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/188swap set/reset priority for DOI2019-01-02T16:21:31ZMartin Jeřábekswap set/reset priority for DOIContinuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition w...Continuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition which it would introduce is still here, so nothing is lost.
Tasks:
- [x] change implementation
- [x] modify tests
- [x] modify documentationISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/208add registers for reading current timestamp2019-01-02T15:24:10ZMartin Jeřábekadd registers for reading current timestampStrictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and t...Strictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and the counter value is inaccessible there - at all. So it would be nice to have read-only access to it via the CAN core in case the integrator forgets to make it accessible from the counter directly again. As a bonus, it will be simpler to handle the timestamps in Linux driver, because it will not have to depend on an external timer.
Will be useful for #158.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/186non-zero error counters with more transmitters2019-01-02T14:59:11ZMartin Jeřábeknon-zero error counters with more transmittersTestcase:
2x ctucanfd, run intensive "cangen" on both interfaces (`cangen -g 0 -f -b -p 100 canX`)
The interfaces go high on RX errors (sometimes up to EP level, but won't cross 128). TX counter is also nonzero, but goes back towards ze...Testcase:
2x ctucanfd, run intensive "cangen" on both interfaces (`cangen -g 0 -f -b -p 100 canX`)
The interfaces go high on RX errors (sometimes up to EP level, but won't cross 128). TX counter is also nonzero, but goes back towards zero faster.
Tasks:
- [ ] is it only in FD mode or also with non-fd frames?
- [ ] is it only in high-load scenarios or also low-load?
- [ ] why isn't Bus Error interrupt (or similar) triggered?
- [ ] maybe try to employ Event Logger (from userspace) to get the exact error type