CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-05-23T12:07:02Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/415Gate level simulation2021-05-23T12:07:02ZIlle, Ondrej, Ing.Gate level simulationCurrently, GHDL does not support Verilog, nor does Vivado support exporting
VHDL timing netlist with VITL. Therefore timing gate level simulation
is not really possible...
However, Vivado should support VHDL models of FPGA cells via "uni...Currently, GHDL does not support Verilog, nor does Vivado support exporting
VHDL timing netlist with VITL. Therefore timing gate level simulation
is not really possible...
However, Vivado should support VHDL models of FPGA cells via "unisim" library.
This should be unit delay simulation.
Following approach might be good:
1. Run Synthesis during "build" phase. Will be done in #212 .
2. Export netlist in VHDL/EDIF format to "test" phase.
3. Have one test configuration (mix of feature, compliance runs), which will
run tests on gates.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/393Functional coverage fix2020-12-09T21:17:47ZIlle, Ondrej, Ing.Functional coverage fixTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/389Datasheet clean-up vol. 22020-10-31T22:14:25ZIlle, Ondrej, Ing.Datasheet clean-up vol. 2Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to dis...Additionally, following things can be cleaned in Datasheet:
1. Rename LOM mode to BMM mode (in CAN standard it is bus monitoring mode)
2. Provide initialization/deinitialization sequence.
3. Add better description of filters (how to distuiguish betwen Base and Extended frames)
4. Add RTR suppression for frame filters.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/387AHB test2023-12-17T20:38:17ZIlle, Ondrej, Ing.AHB testAt the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)At the moment there is missing test for AHB wrapper in CTU CAN FD. It would be good to add one (even if primitive one)Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/374Testbench unification2021-04-23T20:59:39ZIlle, Ondrej, Ing.Testbench unificationAt the moment, there are several different testbenches for CTU CAN FD:
Unit tests - each own TB
Feature - One TB, many tests
Sanity - One TB, no tests
Reference - One TB, different tests based on data sets.
Compliance - One TB,...At the moment, there are several different testbenches for CTU CAN FD:
Unit tests - each own TB
Feature - One TB, many tests
Sanity - One TB, no tests
Reference - One TB, different tests based on data sets.
Compliance - One TB, different tests.
The aim of this task is to merge Feature, Reference and Compliance tests into
a single TB, this would be then the main TB of CTU CAN FD. Unit and Sanity tests
can be kept separate.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/373Test framework cleanup2020-09-20T14:58:37ZIlle, Ondrej, Ing.Test framework cleanupAs most of the tests were re-written and RTL changed extensively, conversions of TCL
files to GHW files with TCL parser is not needed anymore. The aim of this task is to
remove it.As most of the tests were re-written and RTL changed extensively, conversions of TCL
files to GHW files with TCL parser is not needed anymore. The aim of this task is to
remove it.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/370Split sources into two libs2020-09-15T15:41:21ZIlle, Ondrej, Ing.Split sources into two libsTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/369Source code decoupling2020-09-15T15:43:54ZIlle, Ondrej, Ing.Source code decouplingTo make design + TB more modular, following can be done:
1. [x] Split VHDL sources into TB and RTL libraries, avoid using implicit "work" library.
2. [ ] Provide VUnit replacement package, which would allow running TBs also without Vunit.To make design + TB more modular, following can be done:
1. [x] Split VHDL sources into TB and RTL libraries, avoid using implicit "work" library.
2. [ ] Provide VUnit replacement package, which would allow running TBs also without Vunit.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/358Protocol exception feature test2021-02-18T22:16:02ZIlle, Ondrej, Ing.Protocol exception feature testAdd Protocol exception test to verify all combinations of Protocol exception.
This includes following:
1. CAN 2.0 - no protocol exception
2. CAN FD Tolerant - protocol exception on Recessive FDF.
3. CAN FD Enabled - no protocol exception...Add Protocol exception test to verify all combinations of Protocol exception.
This includes following:
1. CAN 2.0 - no protocol exception
2. CAN FD Tolerant - protocol exception on Recessive FDF.
3. CAN FD Enabled - no protocol exception - form error on recessive r0 in CAN FD frames.
4. CAN FD Enabled - protocol exception on Recessive r0 in FD frames.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/336Feature tests extension2019-11-28T17:19:35ZIlle, Ondrej, Ing.Feature tests extensionImplement feature tests for the rest of the registers.Implement feature tests for the rest of the registers.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/311Feature test clean-up2019-11-08T03:03:21ZIlle, Ondrej, Ing.Feature test clean-upRemove obsolete feature tests, modify existing ones to reflect newest expected HW behvaiour.Remove obsolete feature tests, modify existing ones to reflect newest expected HW behvaiour.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/309RX traffic counter test2019-09-28T09:19:24ZIlle, Ondrej, Ing.RX traffic counter testAdd feature test for RX traffic counter.
This one should cover stuff like:
1. RX counter is incremented when frame is received at EOF.
(No need to verify exact position within EOF, this should be done in ISO conformance tests)
2. RX co...Add feature test for RX traffic counter.
This one should cover stuff like:
1. RX counter is incremented when frame is received at EOF.
(No need to verify exact position within EOF, this should be done in ISO conformance tests)
2. RX counter is not incremented when received frame is corrupted by error frame.
3. RX counter is not incremented when frame is transmitted.
4. RX counter is not cleared by COMMAND[TXFRCRST].
5. RX counter is cleared by COMMAND[RXFRCRST].Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/300Add Burst test2020-10-31T20:24:53ZIlle, Ondrej, Ing.Add Burst testAdd test which excercises Read and Write Bursts to the register map! Functions for
invoking bursts are already implemented in CAN Test lib.Add test which excercises Read and Write Bursts to the register map! Functions for
invoking bursts are already implemented in CAN Test lib.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/294Stuff bit on last bit before Stuff count2019-12-02T22:09:47ZIlle, Ondrej, Ing.Stuff bit on last bit before Stuff countTest that when there is Stuff bit on last bit of field preceding Stuff Count,
fixed Stuff bit is not inserted before first bit of Stuff Count.
This also needs to be tested on bit destuffing (RX Datapath).Test that when there is Stuff bit on last bit of field preceding Stuff Count,
fixed Stuff bit is not inserted before first bit of Stuff Count.
This also needs to be tested on bit destuffing (RX Datapath).Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/288Reset value test2019-11-08T03:35:10ZIlle, Ondrej, Ing.Reset value testAdd feature test for reset value.
Now "CAN_FD_registers" contain an array of registers. Add
test which will iterate over the registers, read its content
and compare with its reset value.Add feature test for reset value.
Now "CAN_FD_registers" contain an array of registers. Add
test which will iterate over the registers, read its content
and compare with its reset value.Test improvementsIng. Viktor FúraIng. Viktor Fúrahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/283TXT Buffer priority feature test2019-08-02T16:42:30ZIlle, Ondrej, Ing.TXT Buffer priority feature testPSL coverage revealed that we never even access TX_PRIORITY register.
The aim here is to test whether TX arbitrator selects a frame from TXT
Buffer with the highest priority and sends it, in case of more TXT Buffers
in "READY" state.
I...PSL coverage revealed that we never even access TX_PRIORITY register.
The aim here is to test whether TX arbitrator selects a frame from TXT
Buffer with the highest priority and sends it, in case of more TXT Buffers
in "READY" state.
I would propose sth like:
1. Configure random TXT Buffer priorities.
2. Insert frames to TXT Buffers.
3. Send "set_ready" command to all TXT Buffers.
4. Observe if the other node receives the frames in the expected order.
Regarding point 3, currently "send_TXT_buf_cmd" only supports single buffer at once.
You will either have to modify the function or create an overloaded version
which can set multiple Buffers to Ready at once.
If you would set the buffers "ready" one after another, CAN Core could choose
from buffers which are ready in between the transactions, therefore the "set_ready"
for all buffers needs to be atomic (single bus access).Test improvementsIng. Viktor FúraIng. Viktor Fúrahttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/280Add VCD support to Simulation framework2019-03-14T17:50:20ZIlle, Ondrej, Ing.Add VCD support to Simulation frameworkRight now we have TCL wave files. These are converted to GHW wave files.
However, when debugging e.g. sanity test, simulation performance is very bad
(about two orders of magnitude worse than modelsim).
This is caused by dumping all the ...Right now we have TCL wave files. These are converted to GHW wave files.
However, when debugging e.g. sanity test, simulation performance is very bad
(about two orders of magnitude worse than modelsim).
This is caused by dumping all the waves in GHW file.
Disadvantages:
1. Long simulation time -> Hard to debug.
Advantages:
1. All waves are dumped -> Able to display next wave in the middle of simulation
GHDL also supports dumping in VCD format which may be filtered.
The aims of this task are:
1. [ ] Write parser for TCL files which would create a file that can
be used with "--read-wave-opt=<FILENAME>". GHDL should only dump signals
which are part of this TCL file!
2. [ ] Embed this dumping to Python test framework. There will be two options
for wave files (GHW or VCD), GHW will dump everything and only display
what is in TCL file. VCD will only dump what is in the TCL file and
also display it in GTKWave.
As this is next feature of the test framework (which is quite generic) though
it might be handy to re-factor the test framework before implementing it.
By refactoring I namely mean separating test specific stuff from common
framework/simulation stuff.
@jerabma7 @furavikt What do you think?Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/268Re-write design assertions to PSL2019-08-04T11:42:17ZIlle, Ondrej, Ing.Re-write design assertions to PSLUse PSL assertions instead of VHDL assertions through the RTL sources.
This has one single reason, it is reported in functional coverage report and
we can see the assertion result, otherwise it is just burried in the
code.Use PSL assertions instead of VHDL assertions through the RTL sources.
This has one single reason, it is reported in functional coverage report and
we can see the assertion result, otherwise it is just burried in the
code.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/258Achieve TXT Buffer hazard coverage2019-02-02T12:28:20ZIlle, Ondrej, Ing.Achieve TXT Buffer hazard coverageCurrent TXT Buffer hazard coverage test did not achieve coverage of the hazard situation.
Resolve thisCurrent TXT Buffer hazard coverage test did not achieve coverage of the hazard situation.
Resolve thisTest improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/232Add Timestamp support to CAN Testlib2019-01-20T16:31:12ZIlle, Ondrej, Ing.Add Timestamp support to CAN TestlibAdd support for reading timestamp into CANTest lib.
In: test/lib/CANTestlib.vhd add function: CAN_read_timestamp.
This function will read from TIMESTAMP_LOW_ADR and TIMESTAMP_HIGH_ADR, concatenate the values to
one std_logic_vector, an...Add support for reading timestamp into CANTest lib.
In: test/lib/CANTestlib.vhd add function: CAN_read_timestamp.
This function will read from TIMESTAMP_LOW_ADR and TIMESTAMP_HIGH_ADR, concatenate the values to
one std_logic_vector, and return this vector (as a variable assignment). Since VHDL does not have
64 bit int type, returning as std_logic_vector(63 downto 0) is enough. Also in SW_CAN_Frame_type
this is used as timestamp reference.
Also, add proper function header with comments and argument explanation as in the other functions.
This function will be then used by timestamp test.Test improvementsIng. Viktor FúraIng. Viktor Fúra