CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2019-01-08T20:13:20Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/239Regmap gen saturation fix.2019-01-08T20:13:20ZIlle, Ondrej, Ing.Regmap gen saturation fix.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/231Reset of memory registers2019-01-06T16:36:08ZIlle, Ondrej, Ing.Reset of memory registersRe-work of registers with register map generator brought another bug.
Register modules are not anymore reset by MODE[RST], they are reset only by "res_n" input.Re-work of registers with register map generator brought another bug.
Register modules are not anymore reset by MODE[RST], they are reset only by "res_n" input.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/230CAN FD TX Bit Error detection optimization2019-01-18T17:25:43ZIlle, Ondrej, Ing.CAN FD TX Bit Error detection optimizationStatement of a problem:
CAN FD Transceiver in Data Bit-Rate must detect BIT Error. If value transmitted in Sync differs
from value in Sample Point, Bit error should be detected.
Since Data Bit-Rate might be fast enough, secondary sampl...Statement of a problem:
CAN FD Transceiver in Data Bit-Rate must detect BIT Error. If value transmitted in Sync differs
from value in Sample Point, Bit error should be detected.
Since Data Bit-Rate might be fast enough, secondary sampling mechanism is employed?
What does it mean for Bit error detection in this case?
RX value sampled by delayed sampling point must be compared with TX Data value at the time
of regular sampling point (or TX value that corresponds to the bit where original non-delayed
sample point was).
Secondary sampling point is implemented via shift register where sampling point is piped into this
register. Shift register output at index of ssp_offset is taken as delayed sampling point.
This is OK to create delayed sampling point. Could be optimized somehow, but that is not the point now.
Another shift register is used to store value of TX Data. Shit register output at index of ssp_offset
is taken and this gives us the original TX value at the time of regular sampling point.
What could be optimized is this second shift-register. We don't need to remember whole bit-stream per
clock cycle. We only need to remember values sent in SYNC segments. Proposal is to create small
cache/buffer FIFO-like where upon TX, new data will be appended to the end and upon active
delayed sampled point last data will be read. In Shift-register only the last data are read anyway.
If not, then we missed something and did not execute Bit Error comparison on a bit anyway...
Actually both shift registers have 130 entries. Removing one of them would lower the resource usage
or maybe allow extending the other one...ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/227Documentation clarification - register modifications.2019-01-06T12:49:26ZIlle, Ondrej, Ing.Documentation clarification - register modifications.Explicitly clarify which register can be written only when core is disabled (SETTINGS[ENA]=0).
Out of top of my head for sure BTR, BTR_FD registers.
@jerabma7 @pisa @jnovak What do you think, which others?Explicitly clarify which register can be written only when core is disabled (SETTINGS[ENA]=0).
Out of top of my head for sure BTR, BTR_FD registers.
@jerabma7 @pisa @jnovak What do you think, which others?ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/225after transmitting a Passive Error Frame, the node does not transmit Suspend ...2019-03-14T18:50:38ZMartin Jeřábekafter transmitting a Passive Error Frame, the node does not transmit Suspend TransmissionWhen the node is transmitting a Passive Error Frame, the Passive Error Flag is lenghtened until 6 consecutive bits of the same value are detected (in this case recessive). After that, the 8bit Error Delimiter is transmitted, followed by ...When the node is transmitting a Passive Error Frame, the Passive Error Flag is lenghtened until 6 consecutive bits of the same value are detected (in this case recessive). After that, the 8bit Error Delimiter is transmitted, followed by 3bit Intermission. Now, it should be followed by 8 bits of Suspend Transmission, because the node was a transmitter (of the Passive Error Frame). That is not the case, asi is visible from the waveform. Only 17 bits are before the SOF -- 6 from Error Flag, 8 from Error Delimiter, and 3 from Intermission.
The SJA is now also Error Passive (it sends Passive Error Frame in reaction to not receiving ACK for its frame, which is expected in this situation). The thing that it sends in reaction to the SOF is not an Error Frame, but an Overload Frame (because the SOF is detected in 2nd bit of Intermission).
![nosusp](/uploads/db10a10da94e2d5586301950ce654687/nosusp.png)ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/215Config options on top2019-08-04T11:35:49ZIlle, Ondrej, Ing.Config options on topBring configuration options to top level generics so that all generic options are set on single
level of hierarchy.Bring configuration options to top level generics so that all generic options are set on single
level of hierarchy.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/214Add configurable reset2019-08-04T11:55:54ZIlle, Ondrej, Ing.Add configurable resetModify all source codes to have configurable re-set polarity.Modify all source codes to have configurable re-set polarity.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/211Add VHDL configurations2019-03-18T22:28:18ZIlle, Ondrej, Ing.Add VHDL configurationsAdd VHDL configuration for each file from "src".Add VHDL configuration for each file from "src".ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/210Prescaler FSM rework2019-03-19T22:41:07ZIlle, Ondrej, Ing.Prescaler FSM reworkSeparate Prescaler FSM into stand-alone module.
Avoid ugly logic for sync trigger generation in h_sync state.Separate Prescaler FSM into stand-alone module.
Avoid ugly logic for sync trigger generation in h_sync state.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/208add registers for reading current timestamp2019-01-02T15:24:10ZMartin Jeřábekadd registers for reading current timestampStrictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and t...Strictly speaking the timestamp is from external source, which should provide CPU access to the value itself (either read-only or dead-write). However, the engineers at Xilinx apparently reasoned similarly when designing Xilinx CAN and the counter value is inaccessible there - at all. So it would be nice to have read-only access to it via the CAN core in case the integrator forgets to make it accessible from the counter directly again. As a bonus, it will be simpler to handle the timestamps in Linux driver, because it will not have to depend on an external timer.
Will be useful for #158.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/207Design decoupling2019-01-05T00:01:41ZIlle, Ondrej, Ing.Design decouplingThe aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x...The aim of this task is to decouple the design into more sub-blocks thus achieving better readability.
1. [x] Move TXT Buffer FSM to a separate entity.
2. [x] Move TX Arbitrator FSM to a separate entity.
3. [x] Generic CRC entity.
3. [x] Move RX Buffer FSM to a separate entity
4. [x] Create generic instances of Range Filter and Bit Filter.
5. [x] Generic instance of Re-synchronizer in BusSync.
6. [x] Create generic Interrupt Module and instantiate array of these modules.
7. [x] Move all CRCs and CRC mux logic in CAN Core to separate wrapper!
8. [x] Re-factor Bit Stuffing
9. [x] Re-factor Bit De-stuffing
6. [x] Re-organize SRC folder structure.
7. [x] Accustomize wave files for newly introduced signals.
8. [x] Modify documentation (file names, accustomize pictures)
ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/204SSP offset2019-01-06T10:30:16ZIlle, Ondrej, Ing.SSP offsetImplement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for S...Implement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for SSP offset:
1. Use only measured value
2. Use only SW offset.
3. Use measured value + SW offset.
Addition of trv_delay and SW SSP offset will be realized inside Bus Sampling
module, since shift registers for secondary sampling are implemented there.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/203Protocol exception behaviour2019-08-04T11:40:32ZIlle, Ondrej, Ing.Protocol exception behaviourAdd Flag of Protocol exception behaviour as defined in ISO conformance test plan.
Protocol exception shall be like a flag and set when:
drv_fd_ena is set to 0 and r0 (EDL) bit of CAN 2.0 frame is received RECESSIVE.
drv_fd_ena is set to ...Add Flag of Protocol exception behaviour as defined in ISO conformance test plan.
Protocol exception shall be like a flag and set when:
drv_fd_ena is set to 0 and r0 (EDL) bit of CAN 2.0 frame is received RECESSIVE.
drv_fd_ena is set to 1 and r0 bit of CAN FD frame is received RECESSIVE.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/195TX Buffer explicit memory2018-10-31T20:22:24ZIlle, Ondrej, Ing.TX Buffer explicit memoryAs RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.As RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/194Protocol Control rework2019-08-02T16:42:29ZIlle, Ondrej, Ing.Protocol Control reworkRe-write Protocol control into separate FSMs to achieve higher modularity, cleaner design and possible lower ALM usage.Re-write Protocol control into separate FSMs to achieve higher modularity, cleaner design and possible lower ALM usage.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/188swap set/reset priority for DOI2019-01-02T16:21:31ZMartin Jeřábekswap set/reset priority for DOIContinuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition w...Continuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition which it would introduce is still here, so nothing is lost.
Tasks:
- [x] change implementation
- [x] modify tests
- [x] modify documentationISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/84Generate VHDL registers from IP-XACT2018-12-09T16:30:04ZIlle, Ondrej, Ing.Generate VHDL registers from IP-XACTIn actual state (8.2.2018) the VHDL package file is generated by pyXact, C header file is generated by pyXact and Lx documentation.
The aim of this task is to create an extension of pyXact and additionally generate VHDL structure which ...In actual state (8.2.2018) the VHDL package file is generated by pyXact, C header file is generated by pyXact and Lx documentation.
The aim of this task is to create an extension of pyXact and additionally generate VHDL structure which will include all registers
(maybe two structures, one for read, one for write direction). The process for memory access to these structures must be generated
and instantiated as a sub-module in the can-fd registers.
Such a module would on one side need a memory bus, on the other side, two register structures (one for written and second for read data).
Generated memory access processes would also generate reset values. It would use the same generated address and bitfield constants as it is using now!
The instance of this module would then connect to Driving bus, Status bus and other signals which are driven from/to the registers.
The actual question is how to deal with the side-effects which set the signals at the moment. These are following:
1. Interrupt_vector_erase -> This wont be a problem by that time since interrupt vector erase by read will be replaced.
2. Generic support such as "sup_filtB", I dont know any way how to set this dependency in IP-XACT.
3. RX_buff_read_first -> How should we read data from the RX FIFO then?? I assume this will be a problem, since we cant afford to create a
next register for moving to the next word by user write. This would create additional delay on the data read!
Logically the next step after this task would be to replace the Driving Bus and status bus in the whole design by these two structures and use attributes of these structures instead of local aliases. This would allow to drop the index documentation and it would simplify the design, since delection of an element from the registers would immediately reflect to missing element in the structure and thus
problem in compilation of any file which would need it!ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/83Overload frame2019-08-04T11:30:02ZIlle, Ondrej, Ing.Overload frameCAN FD ISO standard requires MAC sub-layer to provide means for invoking of Overload frame.
CAN FD ISO standard requires MAC sub-layer to provide means for invoking of Overload frame.
ISO optimizations