CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2019-02-02T11:15:18Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/200Bring-up GHDL functional coverage.2019-02-02T11:15:18ZIlle, Ondrej, Ing.Bring-up GHDL functional coverage.The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated ...The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated in a coverage output.
4. [x] Add PSL coverage gatherhing settings to config file
5. [x] Create PSL statement directly to directory with functional coverage without copyingFunctional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/201RX Buffer functional coverage2019-02-08T15:17:15ZIlle, Ondrej, Ing.RX Buffer functional coverageImplement functional coverage for RX FIFO:
At least following cases should be covered:
1. [x] Buffer empty
2. [x] Buffer full
3. [x] Buffer overflow
4. [x] Buffer read-write at the same time
5. [x] Buffer read-write just after/before ea...Implement functional coverage for RX FIFO:
At least following cases should be covered:
1. [x] Buffer empty
2. [x] Buffer full
3. [x] Buffer overflow
4. [x] Buffer read-write at the same time
5. [x] Buffer read-write just after/before each other (one clock cycle)
6. [x] Data overrun occurs.
7. [x] Read by burst (memory pointer muxed).
8. [x] Storing SOF timestamp (in FSM).
9. [x] Storing EOF timestamp (in FSM).
10. [x] Storing RTR frame
11. [x] Storing Frame with 1, 2, 3 and 16 memory words for data.
12. [x] Stashing frame based on memory full.
13. [x] Stashing frame based on error frame (rec_abort).
14. [x] Buffer reset by SW.Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/220TXT Buffer functional coverage2019-02-02T12:31:58ZIlle, Ondrej, Ing.TXT Buffer functional coverageImplement functional coverage for TXT Buffer.
At least following situations should be covered:
1. [x] Buffer in each FSM state (empty, ready, tx_prog, ab_prog, aborted, failed, OK).
2. [x] Buffer set ready command.
3. [x] Buffer set abo...Implement functional coverage for TXT Buffer.
At least following situations should be covered:
1. [x] Buffer in each FSM state (empty, ready, tx_prog, ab_prog, aborted, failed, OK).
2. [x] Buffer set ready command.
3. [x] Buffer set abort and simultaneous HW command from CAN Core (this is what victor writes test for).Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/262Interrupt Manager functional coverage2019-02-23T20:57:19ZIlle, Ondrej, Ing.Interrupt Manager functional coverageAdd functional coverage for each type of interrupt and also for possible simultaneous
set-clear of the same interrupt.Add functional coverage for each type of interrupt and also for possible simultaneous
set-clear of the same interrupt.Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/263TX Arbitrator functional coverage2019-02-28T18:13:56ZIlle, Ondrej, Ing.TX Arbitrator functional coverageAdd functional coverage to TX arbitrator for following things:
1. [x] Locking the Data by CAN Core.
2. [x] Each buffer selected for transmission and Locking from each Buffer.
3. [x] Unlocking the data.
4. [x] Change of selected TXT Buffe...Add functional coverage to TX arbitrator for following things:
1. [x] Locking the Data by CAN Core.
2. [x] Each buffer selected for transmission and Locking from each Buffer.
3. [x] Unlocking the data.
4. [x] Change of selected TXT Buffer to another buffer, while both buffers are Ready (priority change).
5. [x] Change of selected TXT Buffer to another buffer, first buffer became non-Ready.
6. [ ] Two buffers with equal priority ready.
7. [x] All buffers Ready.
8. [x] Assertion on: Never have LOCK when Buffer is not ready!
9. [ ] Assertion on: Change of selected Buffer. Buffer available should go low for three cycles and then high
again.
10. [x] Selected buffer changed (between transmissions, txtb_changed).
11. [x] Buffer selected, Load started, but Timestamp is not reached (Waiting for transmission at given time).Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/264Prescaler Functional coverage2020-12-10T22:36:57ZIlle, Ondrej, Ing.Prescaler Functional coverageAdd PSL cover points for at least:
1. [ ] Hard-synchronisation
2. [ ] Re-synchronisation with e > 0
3. [ ] Re-synchronisation with e < 0
4. [ ] Re-synchronisation with e < SJW
5. [ ] Re-synchronisation with e > SJW
6. [ ] Re-synchronisat...Add PSL cover points for at least:
1. [ ] Hard-synchronisation
2. [ ] Re-synchronisation with e > 0
3. [ ] Re-synchronisation with e < 0
4. [ ] Re-synchronisation with e < SJW
5. [ ] Re-synchronisation with e > SJW
6. [ ] Re-synchronisation shorter than IPT
7. [ ] Hard-synchronisation during SYNC
8. [ ] Hard-synchronisation during PROP
9. [ ] Hard-synchronisation during PH1
10. [ ] Hard-synchronisation during PH2
11. [ ] No PROP segment configured (prop=0)
12. [ ] No PH1 segment configured (ph1=0)
13. [ ] Switch from Nominal Bit-rate to Data
14. [ ] Switch from Data Bit-rate to Nominal
15. [ ] Re-synchronisation in the Bit where switch occured (up)
16. [ ] Re-synchronisation in the Bit where switch occured (down).
17. [ ] Resynchronisation edge with e>0 for Transmitter (no resync. should be done).Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/267Memory registers functional coverage2019-02-24T17:38:47ZIlle, Ondrej, Ing.Memory registers functional coverageExtend the Register map generator with insertion of functional coverage PSL endpoints.
Following PSL statements should be added:
1. Write statements for each Writable register.
2. Read statement for each Readable register.
This stateme...Extend the Register map generator with insertion of functional coverage PSL endpoints.
Following PSL statements should be added:
1. Write statements for each Writable register.
2. Read statement for each Readable register.
This statement should be optional in register map generator (Insert / Not insert).Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/273Bus sampling functional coverage2020-12-12T15:10:14ZIlle, Ondrej, Ing.Bus sampling functional coverageImplement functional coverage to the bus sampling module.
1. [ ] Sampling a bit by Normal sampling as well as tripple sampling.
2. [ ] Sampling with Nominal sample.
3. [ ] Sampling with Data sample.
4. [ ] Sampling with Secondary sample...Implement functional coverage to the bus sampling module.
1. [ ] Sampling a bit by Normal sampling as well as tripple sampling.
2. [ ] Sampling with Nominal sample.
3. [ ] Sampling with Data sample.
4. [ ] Sampling with Secondary sample.
5. [ ] Secondary sampling with all three types of SSP offset.
6. [ ] Secondary sampling with Offset only and offset is 0 -> Should be equal to Data sample.
7. [ ] Secondary sampling configured to Maximum possible value.
8. [ ] Assertion for secondary sampling point, that it is delayed only up to its saturation value,
9. [ ] Secondary sample point offset + trv_delay forming more than ssp saturation.
10. [ ] Assertions on TX Data cache (still to be thought of)
11. [ ] Bit error detection in Nominal, Data and Secondary sample.Functional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/290PSL post-processing2019-09-26T21:29:19ZIlle, Ondrej, Ing.PSL post-processingWith incrementing amount of PSL assert/cover statements there simulation time grows.
Since "cover" statements are part of our RTL (not TB), they also contribute to simulation
time significantly. But cover/assert statements are not needed...With incrementing amount of PSL assert/cover statements there simulation time grows.
Since "cover" statements are part of our RTL (not TB), they also contribute to simulation
time significantly. But cover/assert statements are not needed for someone who is integrating
the RTL and assumes RTL is already tested...
The idea is to create RTL post-processing which would remove PSL statements from RTL.
This is easily doable via Python script, however PSL points must be unified through the
design.
1. [x] Unify PSL points (add common comments for start/end of PSL sections).
2. [x] Implement script which drops PSL section from all RTL.
3. [x] Implement script which copies RTL to new folder and creates "released" version of RTL.
4. [x] Implement script which append PDF docs to new RTL.Functional coverage