CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2021-09-25T09:49:50Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/436Time-base generation by CTU CAN FD2021-09-25T09:49:50ZIlle, Ondrej, Ing.Time-base generation by CTU CAN FDCurrently, CTU CAN FD receives external time-base via Timestamp input.
ISO11898-1 2015 defines that a CAN implementation shall provide such time-base.
The goal of this issue is to implement such time-base as optional block which
could ...Currently, CTU CAN FD receives external time-base via Timestamp input.
ISO11898-1 2015 defines that a CAN implementation shall provide such time-base.
The goal of this issue is to implement such time-base as optional block which
could be included by top-level generic.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/435Edge filtering during bus integration2021-09-19T16:09:19ZIlle, Ondrej, Ing.Edge filtering during bus integrationISO11898-1 2015 defines an option to filter detected edges when node is in bus-idle state.
Currently, this is not implemented.ISO11898-1 2015 defines an option to filter detected edges when node is in bus-idle state.
Currently, this is not implemented.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/416Formal verification of CTU CAN FD2022-11-07T22:51:39ZIlle, Ondrej, Ing.Formal verification of CTU CAN FDThe scope of this issue is following:
1. Build docker image with Symbyosis + GHDL plugin
2. Run formal verification of CTU CAN FD RTL.The scope of this issue is following:
1. Build docker image with Symbyosis + GHDL plugin
2. Run formal verification of CTU CAN FD RTL.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/414Linux driver verification2021-05-17T12:30:31ZIlle, Ondrej, Ing.Linux driver verificationCurrently, there are no tests for Linux driver itself. Automated FPGA build
run in CTU synthesizes latest RTL and runs set of communication tests with SJA1000.
This is good basic sanity test that "communication works". This test will not...Currently, there are no tests for Linux driver itself. Automated FPGA build
run in CTU synthesizes latest RTL and runs set of communication tests with SJA1000.
This is good basic sanity test that "communication works". This test will not properly
test following conditions:
1. Error handling, REC/TEC readout towards proper value (there was a bug in driver where
REC/TEC readout was swapped).
2. Arbitration lost handling.
3. Fault-state changes (to active, passive and bus-off, reintegration and joining the bus
back-on).
This task deals with creating set of tests which will run as part of CI pipeline.
These tests shall verify the functionality of Linux driver and all its corner-cases.
Several approaches are possible:
1. Use Qemu + VPCIe framework and do co-simulation of GHDL + Qemu (virtual Linux + RTL simulation).
2. Use some framework for linux driver testing (e.g. SymDrive, Linux driver test...)Linux driverhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/407Adjust driver to read actual number of TXT buffers.2022-01-05T12:03:22ZIlle, Ondrej, Ing.Adjust driver to read actual number of TXT buffers.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/404SSP at last bit - clarification2021-02-18T18:15:12ZIlle, Ondrej, Ing.SSP at last bit - clarificationIt should be clarified whether SSP which occurs just before SP
of CRC delimiter and detect bit error, shall also cause bit error!
ISO spec says that SSP shall be stopped at SP of CRC delimiter!
Therefore if SSP is configured so that it ...It should be clarified whether SSP which occurs just before SP
of CRC delimiter and detect bit error, shall also cause bit error!
ISO spec says that SSP shall be stopped at SP of CRC delimiter!
Therefore if SSP is configured so that it occurs just before SP
of CRC delimiter, it shall IMHO still detect bit error. This is
not the case at the moment. Bit error is detected, captured, but
ignored upon upcoming sample point in CTU CAN FD.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/403CAN Clock2021-06-19T15:53:23ZIlle, Ondrej, Ing.CAN ClockSplit CAN FD IP Core into two clock domains:
1. CAN Clock
2. System Clock
This is needed to meet oscillator tolerance requirements of CAN Bus. If this is not done, then
also Memory bus needs to be clocked from oscillator which meets bit...Split CAN FD IP Core into two clock domains:
1. CAN Clock
2. System Clock
This is needed to meet oscillator tolerance requirements of CAN Bus. If this is not done, then
also Memory bus needs to be clocked from oscillator which meets bit timing requirements on CAN bus!
Typical MCU usage would however require two clock domains!
1. [ ] Update System architecture with decision how it will be done (list all signals crossing CDC, and their CDC handling protocol). Decide about best/worst case clock frequencies ratio!
2. [ ] Update User-guide to take "CAN clock" into account.
3. [ ] Implement the change in RTL.
4. [ ] Debug existing tests.
5. [ ] Create tests / regressions which verify minimal/maximal ratios of clock frequencies.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/293Retransmitt counter clear by Set abort2021-02-18T18:15:34ZIlle, Ondrej, Ing.Retransmitt counter clear by Set abortIf TXT Buffer is aborted and it is the buffer which is acutally used for transmission, or it was the last buffer which was used for transmission, retransmitt counter must be cleared, otherwise counter value stays hanging there for next f...If TXT Buffer is aborted and it is the buffer which is acutally used for transmission, or it was the last buffer which was used for transmission, retransmitt counter must be cleared, otherwise counter value stays hanging there for next frames!ISO optimizations