CTU CAN FD IP Core issueshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues2017-12-20T17:49:25Zhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/48 and 16 bit access extension2017-12-20T17:49:25ZIlle, Ondrej, Ing.8 and 16 bit access extensionTo have proper access one Avalon bus, byte enable signal must be added into
the CAN Top level and registers module.
Actual implementation of the IP Core supports only full 32 bit accesses. The origin of the implementation is in the test...To have proper access one Avalon bus, byte enable signal must be added into
the CAN Top level and registers module.
Actual implementation of the IP Core supports only full 32 bit accesses. The origin of the implementation is in the test platform where byte enable support was not needed. On the road to the full compatibility with the Avalon spec, byte enable signal must be added. Inactive bits of this signal will mask out the write data and not write the bytes which are forbidden for writing by byte-enable signal. Adding byte enable signal will add support for accessing the registers from uint8_t and uint16_t types in C. All side effects (like clearing interrupt vector by performing read) must be also masked out by byte enable signal.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/6Retransmitt frame dropping2017-12-27T23:40:15ZIlle, Ondrej, Ing.Retransmitt frame droppingThe actual implementation rettransmitts the frame once the Core lost arbitration or error occured. The repetition of the re-transmission can be limited by the user. However if the retransmitt limit option is disabled the frame will re-tr...The actual implementation rettransmitts the frame once the Core lost arbitration or error occured. The repetition of the re-transmission can be limited by the user. However if the retransmitt limit option is disabled the frame will re-transmitt forever and might possibly block this core for longer time. The aim of this task is to detect if higher priority frame is present in either of TX Frames before re-transmitting the frame. If yes, the actual frame should be dropped, and the higher priority frame should be loaded to CAN Core for transmission. The behaviour must be configurable from user-registers. Thus user can choose whether the frame will be dropped or re-transmitted in presence of higher priority frame in the buffer. The implementation involves comparison between the actual frame identifier in the CAN Core and the Identifiers in the TX buffers. This feature will be implemented in the TX Arbitrator circuit or Protocol Control FSM.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/10TX buffer unit test2018-04-15T10:53:59ZIlle, Ondrej, Ing.TX buffer unit testRewrite the TX buffer unit test after change of TX Data handlingRewrite the TX buffer unit test after change of TX Data handlingTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/4364 bit timestamp alignemt2018-01-02T22:50:25ZIlle, Ondrej, Ing.64 bit timestamp alignemtAccording to doc. Pisa Pavel the actual layout of the CAN frame in the RX Buffer and TX Buffer is not
proper for SW implementation. Timestamp words are located at relative address offsets 1 and 2, thus
the 64 bit value of timestamp is no...According to doc. Pisa Pavel the actual layout of the CAN frame in the RX Buffer and TX Buffer is not
proper for SW implementation. Timestamp words are located at relative address offsets 1 and 2, thus
the 64 bit value of timestamp is not 64 bit word aligned.
The proposed solution for this to move the identifier word into the second word of the frame and leave the
Timestamp in the third and fourth word of the frame. This involves following changes:
- RX Buffer storing change
- TX Arbitrator decoding change
- CAN Test lib change in functions for storing TX frame and reading RX frameBug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/19Error code captur register2018-01-05T10:02:11ZIlle, Ondrej, Ing.Error code captur registerAdd Error code capture register as in SJA1000
according to where in the frame error ocurred.Add Error code capture register as in SJA1000
according to where in the frame error ocurred.Ille, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/33Add status bits2017-12-28T10:57:42ZIlle, Ondrej, Ing.Add status bitsNew optimizations involved adding pre-synthesis generics such as : filter support and tx_time support.
It is necessary to add status bit indicating support of these features to the SW.New optimizations involved adding pre-synthesis generics such as : filter support and tx_time support.
It is necessary to add status bit indicating support of these features to the SW.FPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/35Synthesis automation2017-12-20T00:02:10ZIlle, Ondrej, Ing.Synthesis automationCreate a script which would perform automatic synthesis of the Core with several different settings
, gather the results and provide the outcome in structured mannerCreate a script which would perform automatic synthesis of the Core with several different settings
, gather the results and provide the outcome in structured mannerDesign automationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/38RX and TX Data register restructuring2017-12-19T16:23:30ZIlle, Ondrej, Ing.RX and TX Data register restructuringCreate two distinct memory locations in the register map which would have RX_DATA and TX_DATA which will be bit aligned.
This will reduce decoder resources.
Update documentation
Update Can test library to be compatible with new register mapCreate two distinct memory locations in the register map which would have RX_DATA and TX_DATA which will be bit aligned.
This will reduce decoder resources.
Update documentation
Update Can test library to be compatible with new register mapFPGA resource optimizationIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/39Code formatting - testbench2018-04-06T12:52:27ZIlle, Ondrej, Ing.Code formatting - testbenchMake sure that whole CAN Test framework has unique formatting of source code.Make sure that whole CAN Test framework has unique formatting of source code.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/42Sanity test frame counter2018-02-17T17:33:13ZIlle, Ondrej, Ing.Sanity test frame counterAdd counter for overall amount of frames that went sucesfully on the bus, to have little estimate on how big
test coverage does sanity test haveAdd counter for overall amount of frames that went sucesfully on the bus, to have little estimate on how big
test coverage does sanity test haveTest maintenanceIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/50IP XACTL for register map2018-01-23T13:38:18ZIlle, Ondrej, Ing.IP XACTL for register mapGenerate IP-XACTL XML file for register map from Cactus 2 software.Generate IP-XACTL XML file for register map from Cactus 2 software.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/49Kaktus2 register map2018-01-23T13:38:35ZIlle, Ondrej, Ing.Kaktus2 register mapCreate project in Kaktus2 software and describe the register map of CAN FD IP Core in its actual version
in this software.Create project in Kaktus2 software and describe the register map of CAN FD IP Core in its actual version
in this software.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/51VHDL registers generation2018-01-23T13:38:46ZIlle, Ondrej, Ing.VHDL registers generationExtend the pyxactl tool from https://github.com/olofk/ipyxact
with generation of VHDL constants for CAN FD register map constants.
This includes bit meanings as well as register addresses.Extend the pyxactl tool from https://github.com/olofk/ipyxact
with generation of VHDL constants for CAN FD register map constants.
This includes bit meanings as well as register addresses.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/52C header for driver generation2018-01-27T22:05:24ZIlle, Ondrej, Ing.C header for driver generationExtend the IP XACTL tool from https://github.com/olofk/ipyxact
with generation of header file for Socket CAN driver.
Header file should contain unions for register describtion,
access macros, structures for CAN frame description (either...Extend the IP XACTL tool from https://github.com/olofk/ipyxact
with generation of header file for Socket CAN driver.
Header file should contain unions for register describtion,
access macros, structures for CAN frame description (either custom or overtaken from SocketCAN).Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/53Register map documentation2018-02-06T22:03:11ZIlle, Ondrej, Ing.Register map documentationKaktus2 can generate HTML documentation from register maps.
Either replace the register map in Lyx documentation with HTML reference,
or extend the tool from https://github.com/olofk/ipyxact
with Generation of Lyx Chapter which will cont...Kaktus2 can generate HTML documentation from register maps.
Either replace the register map in Lyx documentation with HTML reference,
or extend the tool from https://github.com/olofk/ipyxact
with Generation of Lyx Chapter which will contain the same chapter
structure as actual Register map chapter.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/61Prepare the actual documentation for transfer to the register map generation2018-02-06T18:52:25ZIlle, Ondrej, Ing.Prepare the actual documentation for transfer to the register map generationThe actual format of the register map documentation can not be generated
from IP-XACT without loss of information in the docu.
Move all the tables, pictures which are not going to be generated by the
script from IP-XACT into a separate ...The actual format of the register map documentation can not be generated
from IP-XACT without loss of information in the docu.
Move all the tables, pictures which are not going to be generated by the
script from IP-XACT into a separate chapters!
This includes:
RX Data format value into separate chapter describing frame format which will be generated from CAN_FD_frame_format register map
of IP-XACT.
TX Data format
RX Buffer memory layout picture.
Logger register values for EVENT_TYPE.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/708 bit register replacement2018-02-06T15:47:21ZIlle, Ondrej, Ing.8 bit register replacementSince the actual implementation of registers is 32 bit there is set of dummy addresses defined in the IP-XACT.
This duplicity is not very good, and was used only temporarily not to have too many changes at the same time!
VHDL package fo...Since the actual implementation of registers is 32 bit there is set of dummy addresses defined in the IP-XACT.
This duplicity is not very good, and was used only temporarily not to have too many changes at the same time!
VHDL package for register map should be re-generated with address offsets from 8 bit register map, the registers
module implementation should be updated and test framework should be modified accordingly.
The advantage of the legacy approach resulted in C header generator which is able to group registers into
bitfield structures of 8,16,32 bits. Thus the update can be done only in HW while the SW header file generator
must only replace the address lookup mechanism with name concatenation of original registers.Single source approachIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/57Literal replacement2018-01-24T18:39:09ZIlle, Ondrej, Ing.Literal replacementResearch the source codes of the CAN Core and CAN Test framework
and find places where literals are used. Replace the literals
with constants defined in CANconstants.vhd or another stand-alone
library.Research the source codes of the CAN Core and CAN Test framework
and find places where literals are used. Replace the literals
with constants defined in CANconstants.vhd or another stand-alone
library.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/58Interrupt register restructuring2018-04-05T10:48:23ZIlle, Ondrej, Ing.Interrupt register restructuringExtend the interrupt register according to discussions with doc. Pavel Píša. Probably the best will be to move it to separate memory location.Extend the interrupt register according to discussions with doc. Pavel Píša. Probably the best will be to move it to separate memory location.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/46Byte enable test2018-07-12T17:39:37ZIlle, Ondrej, Ing.Byte enable testAdd test coverage for new Byte enable functionality into feature testsAdd test coverage for new Byte enable functionality into feature testsTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/63Identifier restructuring2018-04-05T10:48:23ZIlle, Ondrej, Ing.Identifier restructuringIt is more beneficial to swap the BASE and EXTENDED part of the identifier in the registers. BASE identifier should
be at the lowest bits while the EXTENDED should be at the highest bitsIt is more beneficial to swap the BASE and EXTENDED part of the identifier in the registers. BASE identifier should
be at the lowest bits while the EXTENDED should be at the highest bitsSocket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/64Version register2018-02-07T18:51:42ZIlle, Ondrej, Ing.Version registerAdd version register into the Core register map to distinguish between various versions of the CAN controller.
The most appropriate register for this would be uppest 16 bits of the DEVICE_ID registerAdd version register into the Core register map to distinguish between various versions of the CAN controller.
The most appropriate register for this would be uppest 16 bits of the DEVICE_ID registerSocket CAN release featuresIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/65RX Buffer memory valid vector2018-04-05T10:48:23ZIlle, Ondrej, Ing.RX Buffer memory valid vectorRemove memory valid vector on RX Buffer. It is not neccessary and it will save some logic.
When the RX Buffer is empty (read_pointer = write_pointer) all zeroes should be returned on the output.Remove memory valid vector on RX Buffer. It is not neccessary and it will save some logic.
When the RX Buffer is empty (read_pointer = write_pointer) all zeroes should be returned on the output.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/67Optimize the RX Buffer message mark2018-02-21T09:38:36ZIlle, Ondrej, Ing.Optimize the RX Buffer message markRemove the message mark vector since it will consume lot of logic if the buffer size is significant.
Replace it with FSM which will substract the message count value once the whole frame is read (use additional counter which is filled at...Remove the message mark vector since it will consume lot of logic if the buffer size is significant.
Replace it with FSM which will substract the message count value once the whole frame is read (use additional counter which is filled at the time of FRAME_FORM read). Do not forget to clear the FSM during the reset and during the Release Receive Buffer.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/66Store number of words to read (from RX Buffer on current frame) into the firs...2018-02-09T12:50:19ZIlle, Ondrej, Ing.Store number of words to read (from RX Buffer on current frame) into the first FRAME_FORMAT word.1. Store number of words to read (from RX Buffer on current frame) into the first FRAME_FORMAT word.1. Store number of words to read (from RX Buffer on current frame) into the first FRAME_FORMAT word.Socket CAN release featuresIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/68Separate RX Buffer write pointers2018-05-19T20:58:22ZIlle, Ondrej, Ing.Separate RX Buffer write pointersCreate additional commited write pointer which will be updated when the whole frame is ready for read.Create additional commited write pointer which will be updated when the whole frame is ready for read.Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/69Interrupt register extension2018-04-05T10:48:23ZIlle, Ondrej, Ing.Interrupt register extensionAdd intterrupt for receive buffer not empty.Add intterrupt for receive buffer not empty.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/72TXT Buffer prioritization2018-02-17T14:46:52ZIlle, Ondrej, Ing.TXT Buffer prioritizationIt might be more beneficial to create a priority between two buffers instead of comparing the timestamp values between the two frames! This will additionally save some logic.
The aim of this task is following:
1. Create buffer priority ...It might be more beneficial to create a priority between two buffers instead of comparing the timestamp values between the two frames! This will additionally save some logic.
The aim of this task is following:
1. Create buffer priority in the user registers for each TXT Buffer. All the priority values will be in 1 register to be updated at the same time.
2. TX Arbitrator will always pick a frame from higher priority buffer (assuming it is allowed for transmission and it is not empty). This can be decoded combinationally at one clock cycle and it should consume small amount of logic (small lengths of priority registers).
3. If the core is free, the actual selected buffer will be stored (the same as message source in the actual implementation of TX Arbitrator), and kept until the transmission will finish.
4. The core will propagate the frame to be transmitted from highest priority buffer once its timestamp value is higher than then timestamp of that actual frame.
Problems:
A) What should we do once we have the same priorities set on the buffers?? Possible solution: Use fixed order. E.g. First buffer has higher prority, Second will have the second highest, etc.
B) What to do about a situation when lower timestamp frame (should be transmitted sooner) will be present in the buffer with lower priority? Thus the frame with lower timestamp will be actually transmitted LATER because of the priority! Should we leave this to responsible user/driver designer? Or should we implement some kind of circuit which will detect these conditions and signal them? I assume no, I assume that the buffer priority should be the primary way how ot decide between the buffers and the timestamp only secondary!Socket CAN release featuresIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/48Retransmitt limit to frame swapping accustomization2018-02-17T14:48:39ZIlle, Ondrej, Ing.Retransmitt limit to frame swapping accustomizationProvide additional signal from TX arbitrator which forces erasing of the retransmitt counter in ProtocolControl when another frame was selected due to occurence of frame swapp after error frame or arbitration lost.Provide additional signal from TX arbitrator which forces erasing of the retransmitt counter in ProtocolControl when another frame was selected due to occurence of frame swapp after error frame or arbitration lost.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/73TXT frame status2018-02-17T14:50:10ZIlle, Ondrej, Ing.TXT frame statusIt will be good to provide additional status signals on the TXT Buffers.
The actual implementation provides only "empty bit" on the buffer.
This pretty much fills the function of the "busy bit" since the
"empty bit" is set to 1 when the ...It will be good to provide additional status signals on the TXT Buffers.
The actual implementation provides only "empty bit" on the buffer.
This pretty much fills the function of the "busy bit" since the
"empty bit" is set to 1 when the frame is sucesfully transmitted!
If it is transmitted OK, then no problem.
The new implementation should provide next bit "TX OK" which signalizes
that the frame was transmitted without problem.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/74Whole TXT buffer in SRAM2018-04-05T10:48:23ZIlle, Ondrej, Ing.Whole TXT buffer in SRAMThe TXT Buffer should be completely moved to an SRAM memory!
This means that also FRAME_FORMAT_W and IDENTIFIER_W and TIMESTAMPS words should be placed into the SRAM
memory and not be available on the output in paralell!!
The only paral...The TXT Buffer should be completely moved to an SRAM memory!
This means that also FRAME_FORMAT_W and IDENTIFIER_W and TIMESTAMPS words should be placed into the SRAM
memory and not be available on the output in paralell!!
The only paralell information about buffers will be whether the buffers are allowed, and their priority!
Based on this information the highest priority buffer will be selected, and the timestamp words will be
loaded. If the timestamp is lower, then it will be transmitted!
Then the FRAME_FORMAT and also IDENTIFIERs will be loaded.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/75Extend the TX Buffers to 42018-04-05T10:48:23ZIlle, Ondrej, Ing.Extend the TX Buffers to 4Once the TX Buffer is completely present in the SRAM, and it is completely prioritized, it should be extended to 4 Buffers.
It might be even good to think whether not to create a generic amount of buffer (e.g. 2,3 or 4).
This should pla...Once the TX Buffer is completely present in the SRAM, and it is completely prioritized, it should be extended to 4 Buffers.
It might be even good to think whether not to create a generic amount of buffer (e.g. 2,3 or 4).
This should play along nicely with the buffer prioritization. If the logic vectors are implemented in generic amount, then
the extension should be no problem at all!Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/76Remove use_FD_size_option2018-02-10T16:07:58ZIlle, Ondrej, Ing.Remove use_FD_size_optionWith the proposals for the TXT Buffer optimizations, it is no longer necessary to have use_fd_size option.
Since all the buffers will be in SRAMs it has neglicible effect on the overall core size.With the proposals for the TXT Buffer optimizations, it is no longer necessary to have use_fd_size option.
Since all the buffers will be in SRAMs it has neglicible effect on the overall core size.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/86RX Buffer timestamp options2018-04-05T10:48:23ZIlle, Ondrej, Ing.RX Buffer timestamp optionsOn RX CAN Frame the timestamp is taken at the time when the frame was succesfully transmitted (tran_valid signal).
To allow possible usage for TT_CAN, we should extend the implementation with option to capture the timestamp
on begining o...On RX CAN Frame the timestamp is taken at the time when the frame was succesfully transmitted (tran_valid signal).
To allow possible usage for TT_CAN, we should extend the implementation with option to capture the timestamp
on begining of the RX frame.
How to do it? Add configuration bit which will select the time when to capture the timestamp.
At the start of the transmission additional register will capture the timestamp (do we need whole timestamp ??) No... What part do we need???
Lets. assume CAN baudrates of 10 kbits in both nominal and data (crazy I know). We assume highest possible clock frequency e.g. 1 GHz (even more crazy, but we need to assume some kind of worst-case analysis... )
This gives us 100 000 clock cycles per bit time. If we assume the longest CAN frame to be (1+11+2+18+3+4+512+21+3)*1.2 bits, we approx. 670 bits. If the timestamp would be updated each clock cycle this gives us about 67*10^6 ticks per frame. Thus we need to store mostly 26 bits out of 64.
The question is now what about the retransmission. Should the stored timestamp be captured again during retransmission ?? I assume no...
Then in the RX Buffer we would store 26 bits from the timestamp captured at SOF (be carefull about sof_skip stuff!!) the remaining bits
will be stored directly from timestamp input.
Is this kind of implementation appropriate??Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/79Erase the 32 bit register map2018-02-07T18:19:06ZIlle, Ondrej, Ing.Erase the 32 bit register mapTo make the access truly single source, one version of the register map must be erased from the IP-XACT.To make the access truly single source, one version of the register map must be erased from the IP-XACT.Single source approachhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/80Socket CAN driver low level draft2018-04-05T10:48:23ZIlle, Ondrej, Ing.Socket CAN driver low level draftEither extend the original driver or create a new one for Socket CAN with usage of native Linux structures. Create additional header file include which could be used by Mr. Novak for his project where Linux structures are not present!Either extend the original driver or create a new one for Socket CAN with usage of native Linux structures. Create additional header file include which could be used by Mr. Novak for his project where Linux structures are not present!Socket CAN release features2018-03-15https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/62Unit test consolidation2018-06-08T12:41:38ZIlle, Ondrej, Ing.Unit test consolidationMake sure that all the unit tests are accustomized to the changes done during resource optimizationsMake sure that all the unit tests are accustomized to the changes done during resource optimizationsTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/9RX buffer unit test2018-06-08T12:40:52ZIlle, Ondrej, Ing.RX buffer unit testMake sure that RX buffer unit test run properly after changes in structure of reading the RX data.Make sure that RX buffer unit test run properly after changes in structure of reading the RX data.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/144Event logger unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Event logger unit testFinish event logger unit test. Make sure that it covers expected functionality of
event logger. Debug event logger module if necessary.Finish event logger unit test. Make sure that it covers expected functionality of
event logger. Debug event logger module if necessary.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/13Prescaler unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Prescaler unit testExtend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Extend the prescaler unit test to support the Resychronisation, Hard synchronisation and checking
of bit duration during the bit-rate switching. Emulate the Behaviour of CAN Core with delayed
sampling signals!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/37Protocol control unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Protocol control unit testUpdate Protocol Control unit test to be compatible with serialized data interface to TXT buffer and to RX Buffer.
Make sure that unit test properly covers the CRC calculation of ISO and non-ISO CAN FD.Update Protocol Control unit test to be compatible with serialized data interface to TXT buffer and to RX Buffer.
Make sure that unit test properly covers the CRC calculation of ISO and non-ISO CAN FD.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/130TX Arbitrator pipeline + Hazard unit2018-06-06T13:04:20ZIlle, Ondrej, Ing.TX Arbitrator pipeline + Hazard unitThe latest (End of April 2018) synthesis results in Xilinx and Altera Technologies are limited by (not surprisingly) the same combinational paths. The maximum frequencies are somewhere around 90 - 95 MHz. It would be nice to move to 100 ...The latest (End of April 2018) synthesis results in Xilinx and Altera Technologies are limited by (not surprisingly) the same combinational paths. The maximum frequencies are somewhere around 90 - 95 MHz. It would be nice to move to 100 and above.
The reason for this is following:
1. HW and SW commands are applied simultaneously and are completely asynchronous (not in the clock domain sense, rather in "both can happend at any time without knowing about each other").
2. Due to 1. , SW Commands, HW commands and TXT Buffer priorities and "ready indication" are evaluated combinationally!
Such an evaluation contains following combinational paths:
A) Starts in SW command register and TXT Buffer priorities.
B) Propagates through "priority decoder to "select_buf_index" and "select_buf_avail".
C) These values are used to control flow of TX Arbitrator FSM (e.g. restarting on change of "select_buf_index").
D) TX Arbitrator FSM is loading metadata and timestamp from TXT Buffers. Since It takes one clock cycle for RAM,
propagate data to the output, metadata_pointer in TX Arbitrator must be decoded combinationally! The same condition
which causes TX Arbitrator FSM state transition, must be used to combinationally address word in TXT_Buffer memory
in TXT Buffer word (address) which is needed by successive state of FSM.
E) Due to combinational driver on "metadata_pointer", pointer to TXT RAM is not registered and causes path from A up to
hard-core address decoder in RAM.
3. Combinational paths from 2. cause problems in both Technologies (according to Martin Jerabek in Xilinx SoC, there is RAM problem), and in Altera Cyclone V, first 1000 worst paths (about first 2 ns slack) are caused by these paths.
To bring CTU CAN FD Core this problem must be resolved.
Following solutions are available:
1. Implement pipeline between priority decoder and TX Arbitrator FSM. This would however require additional synchronisation
of HW and SW command in new unit "e.g. Hazard unit to have cool naming..."
2. Simpler solution would be to add new state to TX Arbitrator state machine, which would ALWAYS address metadata pointer
with registered value! This would add next clock cycle to data loading (extend to 4 from 3 clock cycles), however it is
easier solution than Hazard unit. One thing would still remain problematic. Address pointer would need to be set two
clock cycles (two states) before data from its address are needed. This would be a problem in state where state
transition is evaluated based on condition. Such a condition might have different value one clock cycle before,
than during the cycle that causes the transition!Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/126Extend bit stuffing unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Extend bit stuffing unit testAt the moment Bit Stuffing unit test is missing SW modeled behaviour (of either Bit Stuffing or Bit destuffing)
which would calculate bit stuffing in behavioral way.
Add such a model and verify that bit stuffing is always returning the ...At the moment Bit Stuffing unit test is missing SW modeled behaviour (of either Bit Stuffing or Bit destuffing)
which would calculate bit stuffing in behavioral way.
Add such a model and verify that bit stuffing is always returning the same results as this model.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/132interrupt enable/mask/status2018-06-06T13:04:20ZMartin Jeřábekinterrupt enable/mask/statusAt the moment interrupts work as following:
- INT_STAT_RAW: raw intrerupt status, independent of enable/mask (not exposed at the moment)
- INT_STAT = INT_STAT_RAW & INT_ENA (acc to datasheet should be INT_MASK instead)
- irq generated if...At the moment interrupts work as following:
- INT_STAT_RAW: raw intrerupt status, independent of enable/mask (not exposed at the moment)
- INT_STAT = INT_STAT_RAW & INT_ENA (acc to datasheet should be INT_MASK instead)
- irq generated if INT_STAT_RAW & INT_ENA & INT_MASK
Issue 1:
Swapped INT_ENA, INT_MASK.
Issue 2:
The mask sense is reversed. Usually when an interrupt bit is masked, it means that it does *not* cause irq generation.
Issue 3:
The value of INT_MASK is questionable. Basically we have 2 settings doing the same thing (enabling IRQ generation), which is useless (correct me if I am wrong). I would also like more if INT_STAT was completely unmasked, i.e. equal to INT_STAT_RAW.
If the masked variant should be desired, it should be masked solely by INT_ENA and INT_MASK would be removed.
It remains to be decided whether we should have (INT_STAT, INT_STAT_MASKED) or (INT_STAT_RAW, INT_STAT), that is if we keep the masked variant at all.
It could make sense to mask irq generation from particular TX buffers - then the TXBHCI bit would not be set if the particular buffer irqs were masked. Here the unmasked _RAW variant of the status register would not make sense.
However, I do not see much value in this for now, so I would just propose the following:
- remove INT_MASK
- do not mask INT_STATUSBug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/137Remove simulation warnings2018-06-06T13:04:20ZIlle, Ondrej, Ing.Remove simulation warningsSimulation warnings are caused by un-initialized values of signals. Remove them, either initialize
signal values, or find simulation setting which will remove the warnings.Simulation warnings are caused by un-initialized values of signals. Remove them, either initialize
signal values, or find simulation setting which will remove the warnings.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/118Fault confinement unit test2018-06-06T13:04:20ZIlle, Ondrej, Ing.Fault confinement unit testImplement missing unit test for fault confinement circuit.Implement missing unit test for fault confinement circuit.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/81sanity test: distribution of gap between two noise pulses2018-06-06T13:04:20ZMartin Jeřábeksanity test: distribution of gap between two noise pulsesGap between two noise pulses is an interval and IMO follows exponential distribution, not normal. For more exact simulation, this can be reflected (but it's a detail).
On another note, we may use the PRNG implemented in ieee.math_real (...Gap between two noise pulses is an interval and IMO follows exponential distribution, not normal. For more exact simulation, this can be reflected (but it's a detail).
On another note, we may use the PRNG implemented in ieee.math_real (uniform) and then transform it to the desired distribution. On the plus side, we will be able to change the seed. It is a question, however, how the performance will be affected.
Normal: N(m,v) = sqrt(-2.0 * log(u1)) * cos(2*pi*u2) * var + mean [Box-Muller]
Exponential: E(1/beta) = -log(u)*beta
(u from U(0,1))Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/125Consolidate test library2018-06-06T13:04:20ZIlle, Ondrej, Ing.Consolidate test libraryThis issue should cover following topics:
1. Consolidation of CANtestlib.vhd. Add missing comments, format the code properly (4 spaces indent), remove unnecessary
functions
2. Add new set of functions which can be used in "feature t...This issue should cover following topics:
1. Consolidation of CANtestlib.vhd. Add missing comments, format the code properly (4 spaces indent), remove unnecessary
functions
2. Add new set of functions which can be used in "feature test". Due to many changes in the register map, most of the
feature tests are broken. If feature tests will be repaired, and register map changes again, there will be need for
further reparations! This is undesirable. There is an idea to create set of low level functions which access
the registers (sth. like HAL) and feature tests will only use these functions to execute tests. If register map changes,
only test library must be updated, and test code and test logic can remain unchanged!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/103Identifier comparison in Testlib2018-06-06T13:04:20ZIlle, Ondrej, Ing.Identifier comparison in TestlibCAN Test library used in sanity tests is missing comparison of identifier decimal values!CAN Test library used in sanity tests is missing comparison of identifier decimal values!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/112TX Arbitrator unit test2018-06-02T22:02:51ZIlle, Ondrej, Ing.TX Arbitrator unit testTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/110TXT Buffer assertion corruptions2018-04-20T11:46:22ZIlle, Ondrej, Ing.TXT Buffer assertion corruptionsResolve corrupted HW, SW command checks in TXT Buffer in sanity test.Resolve corrupted HW, SW command checks in TXT Buffer in sanity test.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/111Interrupt unit test2018-04-20T11:31:22ZIlle, Ondrej, Ing.Interrupt unit testTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/116Message filter unit test2018-04-15T15:33:34ZIlle, Ondrej, Ing.Message filter unit testCorrect the Message filter unit test with the newest implementation of optional message filters
and re-ordered identifiers!Correct the Message filter unit test with the newest implementation of optional message filters
and re-ordered identifiers!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/97Add driver prefix2018-04-05T10:48:23ZIlle, Ondrej, Ing.Add driver prefixSocket CAN driver should have prefix generated in all constantsSocket CAN driver should have prefix generated in all constantsSocket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/88Unwrap the TX Buffers2018-02-19T12:57:24ZIlle, Ondrej, Ing.Unwrap the TX BuffersRemove BUF_DIR bit and create separate memory location for each TXT buffer in the
Memory map. This is needed for different threads filling more buffers at the same time!Remove BUF_DIR bit and create separate memory location for each TXT buffer in the
Memory map. This is needed for different threads filling more buffers at the same time!Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/90Retransmitt counter fix2018-02-17T15:06:48ZIlle, Ondrej, Ing.Retransmitt counter fixAdd increment of rettransmitt counter when arbitration is lost.Add increment of rettransmitt counter when arbitration is lost.Socket CAN release featuresIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/91Stabilize register map2018-04-05T10:48:23ZIlle, Ondrej, Ing.Stabilize register mapAfter all updates in the register map, go through every register and decide whether its location is final.
Discuss this with Martin and mr. Píša.After all updates in the register map, go through every register and decide whether its location is final.
Discuss this with Martin and mr. Píša.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/92Documentation split2018-04-05T10:48:23ZIlle, Ondrej, Ing.Documentation splitSplit the system architecture Chapter into the general part with block diagrams and written description.
The other chapter will be with Tables describing each circuit. Consider putting the second chapter to Appendix.Split the system architecture Chapter into the general part with block diagrams and written description.
The other chapter will be with Tables describing each circuit. Consider putting the second chapter to Appendix.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/98Logger separation2018-04-05T10:48:23ZIlle, Ondrej, Ing.Logger separationSeparate event logger into stand-alone memory location in IP-XACT to make room for Interrupt registers extension.Separate event logger into stand-alone memory location in IP-XACT to make room for Interrupt registers extension.Socket CAN release featureshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/102Transceiver delay2018-04-20T13:16:01ZIlle, Ondrej, Ing.Transceiver delayTransceiver delay measurement is available directly from the register that is used for measurement.
This means that if user reads the value during the measurement an intermediate value of measuring counter
will be returned. This should b...Transceiver delay measurement is available directly from the register that is used for measurement.
This means that if user reads the value during the measurement an intermediate value of measuring counter
will be returned. This should be fixed. Additional register should be added. This register will be updated once the transceiver delay measurement is finished! Thus it will never happend that user would read random value between
0 and ACTUAL_DELAY.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/105Direct transmission of metadata from TXT Buffer2018-04-06T16:04:00ZIlle, Ondrej, Ing.Direct transmission of metadata from TXT BufferIn the actual implementation, the TX Arbitrator loads the metadata during two clock cycles into internal registers
and stores it to the output. At the start of Frame, CAN Core will lock the buffer, and tranBuffer will store metadata.
Si...In the actual implementation, the TX Arbitrator loads the metadata during two clock cycles into internal registers
and stores it to the output. At the start of Frame, CAN Core will lock the buffer, and tranBuffer will store metadata.
Since now, the whole TXT Buffer is implemented as single RAM memory. Data part of CAN Frame is already loaded from the
TXT Buffer via pointer. Metadata + Identifier are still stored in the internal TX Arbitrator registers, on TX arbitrator
outputs and also in tranBuffer.
The aim of this task is to:
1. Implement storing of metadata during SOF by access to TXT Buffer via pointer, instead of taking data from tranBuffer.
2. Implement loading of Identifier shift registers by access to TXT Buffer via pointer, instead of taking data from the registers.
3. If 1 an 2 are implemented, tranBuffer will be obsolete as well as loading Frame format word and identifier word by
TX Arbitrator (Timestamp still must be loaded though). This will simplify TX Arbitrator implementation and also save
some amount of logic!Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/113Coding style unification2018-07-09T15:20:20ZIlle, Ondrej, Ing.Coding style unificationMake sure that all the synthesizable sources codes have unified coding style with 4 spaces
indent.Make sure that all the synthesizable sources codes have unified coding style with 4 spaces
indent.Wishlisthttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/108Referrence test with Kvaser2018-06-28T17:57:00ZIlle, Ondrej, Ing.Referrence test with KvaserInstall Linux software for Kvaser CAN FD, use it to generate several
custom CAN Frames with different protocol options such as:
Normal, FD, RTR, NO RTR, frame with 15,17,21 bit CRC, with BRS
, without BRS.
Sample the final bit sequence b...Install Linux software for Kvaser CAN FD, use it to generate several
custom CAN Frames with different protocol options such as:
Normal, FD, RTR, NO RTR, frame with 15,17,21 bit CRC, with BRS
, without BRS.
Sample the final bit sequence by logic analyzer, store it to file,
and implement test which will transmitt the same CAN Frames as the
one transmitted by Kvaser, and compare the bit values with
Bit values from Kvaser.
Note that this test should provide some basic level testing with
reference controller in simulation!Test maintenanceIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/154Extend basic unit test run2018-06-13T15:33:31ZIlle, Ondrej, Ing.Extend basic unit test runTest maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/45Feature test consolidation2018-06-13T15:14:20ZIlle, Ondrej, Ing.Feature test consolidationFind out problems in all feature tests after the optimization changes!Find out problems in all feature tests after the optimization changes!Test maintenanceIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/115Hard sync in the EDL2018-05-31T17:27:44ZIlle, Ondrej, Ing.Hard sync in the EDLAccording to CAN FD specification Hard synchronisation should be performed in the EDL bit of CAN FD Frame.
In the actual implementation this Hard synchronisation is omitted since Prescaler did not support
Hard synchronisation in the midd...According to CAN FD specification Hard synchronisation should be performed in the EDL bit of CAN FD Frame.
In the actual implementation this Hard synchronisation is omitted since Prescaler did not support
Hard synchronisation in the middle of CAN Frame. In extreme cases (e.g. setting nominal SJW to 0) this could
cause improper operation and inability to receive CAN FD frames.
The aim of this task is to add Hard-synchronisation in the EDL bit of CAN FD Frame.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/117Remove obsolete config options2018-06-02T21:36:37ZIlle, Ondrej, Ing.Remove obsolete config optionsSince major savings in LUT consumption were achieved, following settings of the Core now become osbolete:
support_be
tx_time_sup
Remove these two options.Since major savings in LUT consumption were achieved, following settings of the Core now become osbolete:
support_be
tx_time_sup
Remove these two options.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/122Set up gitlab continuous integration (CI)2018-05-24T19:23:23ZMartin JeřábekSet up gitlab continuous integration (CI)Set up basic CI/CD to run short sanity test after each commit. For now, use the available shared runner.Set up basic CI/CD to run short sanity test after each commit. For now, use the available shared runner.Continuous integrationMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/123Interrupt enable, mask bug-fix2018-04-19T16:38:12ZIlle, Ondrej, Ing.Interrupt enable, mask bug-fixFix missing propagation of internal "int_mask" and "int_ena_reg" to the output of interrupt manager module.Fix missing propagation of internal "int_mask" and "int_ena_reg" to the output of interrupt manager module.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/127Documentation clarification2018-10-04T18:57:06ZIlle, Ondrej, Ing.Documentation clarificationThe aim of this issue is to make sure all parts of documentation describe the behaviour of Core exactly.
Up to now there are following issues known within this topic:
13. Update DRV Bus and Status bus description!The aim of this issue is to make sure all parts of documentation describe the behaviour of Core exactly.
Up to now there are following issues known within this topic:
13. Update DRV Bus and Status bus description!https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/169Message filter feature test2018-09-21T17:28:07ZIlle, Ondrej, Ing.Message filter feature testAdd feature test which will verify usage of each message filter (A,B,C and Range). Simple
implementation with 4 * 2 frames (one passing, one failing frame for each filter) in single
iteration.
Thisway, code coverage for Memory registers...Add feature test which will verify usage of each message filter (A,B,C and Range). Simple
implementation with 4 * 2 frames (one passing, one failing frame for each filter) in single
iteration.
Thisway, code coverage for Memory registers will improve + new mechanism of ANDed RX Buffer
commands will be verified.Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/59Synthesis warning research2018-09-15T12:25:48ZIlle, Ondrej, Ing.Synthesis warning researchSearch through all the synthesis warnings and resolve them if possible.Search through all the synthesis warnings and resolve them if possible.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/170Unify "others" clause!2018-09-15T12:25:48ZIlle, Ondrej, Ing.Unify "others" clause!Search through Protocol control and operation control and make sure that in all cases
"others" on enumerated types is handled in the same way!Search through Protocol control and operation control and make sure that in all cases
"others" on enumerated types is handled in the same way!Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/128Bus off time2018-09-15T12:25:48ZIlle, Ondrej, Ing.Bus off timeAccording to CAN FD specification, each controller should wait at least 128 occurrences of 11 consecutive bits before transfer from BUS OFF to ERROR ACTIVE.
Actual implementation can force transition from BUS OFF to ERROR ACTIVE by eras...According to CAN FD specification, each controller should wait at least 128 occurrences of 11 consecutive bits before transfer from BUS OFF to ERROR ACTIVE.
Actual implementation can force transition from BUS OFF to ERROR ACTIVE by erasing error counters via CTR_PRES register.
This however does corrupt this rule and allows the controller to come back to life sooner than the spec allows it. This might be desirable for testing purposes, thus this approach won't be removed.
However, to be compliant with the standard, there must exist a way how to restart the controller (from BUS OFF to ERROR ACTIVE) while adhering to CAN Standard. Additional counter must be added to count occurences of 11 consecutive bits (could be separate counter or the one in "operationControl". From SW point of view two bits must be added. REQUEST bit to perform the BUS-OFF to ERROR ACTIVE, and STATUS bit to inform about the final transition upon completion of 128 * 11 condition.
Such a commands could be implemented in COMMAND register and status in FAULT_STATE register, since there are reserved bits available.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/21TODO research2018-07-10T19:41:01ZIlle, Ondrej, Ing.TODO researchSearch through the codes of the CAN Core and find all TODOs which are there.
Identify if these TODOs are relevant and actual...Search through the codes of the CAN Core and find all TODOs which are there.
Identify if these TODOs are relevant and actual...Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/168RX Buffer commands filtration2018-07-10T12:33:07ZIlle, Ondrej, Ing.RX Buffer commands filtrationAdd AND gates on ALL commands which are applied on RX Buffer. Use outcome of Message filter as
second input to AND gate. Note that first command comes at the end of control field when
ID is already received and Mesage filter output is e...Add AND gates on ALL commands which are applied on RX Buffer. Use outcome of Message filter as
second input to AND gate. Note that first command comes at the end of control field when
ID is already received and Mesage filter output is evaluated! All commands are thus applied
when Message filter contains valid values (even rec_abort). rec_ident_in is erased only in SOF
and data are invalid between SOF and ID reception. There are no Commands during this time.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/100Fix the DLC reception2018-07-10T10:49:27ZIlle, Ondrej, Ing.Fix the DLC receptionAccording to the CAN FD specification, if CAN Frame (not CAN FD Frame) is received with DLC of 8 or higher (1000,1001,1010 ...)
it should be interpreted only as 8 bytes !
The actual implementation alllows to accept CAN frame and interpt...According to the CAN FD specification, if CAN Frame (not CAN FD Frame) is received with DLC of 8 or higher (1000,1001,1010 ...)
it should be interpreted only as 8 bytes !
The actual implementation alllows to accept CAN frame and interptret the DLC in the same way as CAN FD Frames.Bug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/163Add sync. chain attributes.2018-07-09T12:08:01ZIlle, Ondrej, Ing.Add sync. chain attributes.VHDL attributes should be set on input synchronisation chain in busSync module like so:
https://forums.xilinx.com/t5/Timing-Analysis/Setting-ASYNC-REG-in-VHDL-for-Two-Flop-Synchronizer/td-p/700175
This can be done by TCL constraints fi...VHDL attributes should be set on input synchronisation chain in busSync module like so:
https://forums.xilinx.com/t5/Timing-Analysis/Setting-ASYNC-REG-in-VHDL-for-Two-Flop-Synchronizer/td-p/700175
This can be done by TCL constraints file, but it is better to have it in VHDL file defined explicitly.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/164Reference test problem2018-06-29T09:28:12ZIlle, Ondrej, Ing.Reference test problemAt the moment, reference test does not have the test properly specified, which causes RX buffer unit
test to be executed instead of reference test!At the moment, reference test does not have the test properly specified, which causes RX buffer unit
test to be executed instead of reference test!Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/129TXT Buffer in bus-off2018-06-28T19:17:34ZIlle, Ondrej, Ing.TXT Buffer in bus-offError frame transmission causes transfer of TXT buffer to either READY (without reaching retransmit limit) or FAILED (when retransmit limit was reached). However if retransmit limit remains disabled (or it is not reached) during transiti...Error frame transmission causes transfer of TXT buffer to either READY (without reaching retransmit limit) or FAILED (when retransmit limit was reached). However if retransmit limit remains disabled (or it is not reached) during transition to bus-off state, the buffer goes back to READY state.
Such a behaviour is logically incorrect! Additional logic should be implemented, that shall force active TXT Buffer to go to FAILED when Error frame transmission causes controller to go to BUS OFF.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/133Endian fix2018-05-19T21:29:22ZIlle, Ondrej, Ing.Endian fixGenerator of C header file for Frame format and register map has
swapped LITTLE ENDIAN and BIG ENDIAN macros!
1. Correct this issue in generator.
2. Re-generate header files.Generator of C header file for Frame format and register map has
swapped LITTLE ENDIAN and BIG ENDIAN macros!
1. Correct this issue in generator.
2. Re-generate header files.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/134Buffer Data endianess2018-05-19T23:46:07ZIlle, Ondrej, Ing.Buffer Data endianessAdd component for swapping of byte endianess for data bytes.
Such a component is needed, because first byte should be stored at address 0x0 , second byte at address 0x1.
This organization is necessary for future DMA possibility which w...Add component for swapping of byte endianess for data bytes.
Such a component is needed, because first byte should be stored at address 0x0 , second byte at address 0x1.
This organization is necessary for future DMA possibility which will read data from lowest address.
Endianess swap should be configurable by generic value!Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/147Timestamp options feature test2018-06-29T11:50:52ZIlle, Ondrej, Ing.Timestamp options feature testImplement feature test which will configure timestamp capturing from both, end and beginning of
frames and verify that timestamp is captured properly!Implement feature test which will configure timestamp capturing from both, end and beginning of
frames and verify that timestamp is captured properly!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/149CAN Test randomization2018-06-09T11:38:22ZIlle, Ondrej, Ing.CAN Test randomizationAdd randomize input to
CAN Test entity (and possibly also to CAN Test wrapper).
During test initialization random index should be selected for each rand_ctr, if this input is true.
This will allow for automated runs of tests with diffe...Add randomize input to
CAN Test entity (and possibly also to CAN Test wrapper).
During test initialization random index should be selected for each rand_ctr, if this input is true.
This will allow for automated runs of tests with different data!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/151Fix ALC2018-06-06T11:31:00ZIlle, Ondrej, Ing.Fix ALCRe-enable Arbitration lost capture functionality.
Modify IP-XACT documentation.Re-enable Arbitration lost capture functionality.
Modify IP-XACT documentation.Bug fixinghttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/152ipyxact_parser is checked in as a submodule, but not declared in .gitmodules2018-06-06T12:54:12ZMartin Jeřábekipyxact_parser is checked in as a submodule, but not declared in .gitmodulesAdd as a submodule. Now recursive clone fails.
```
fatal: No url found for submodule path 'modules/CTU_CAN_FD/scripts/pyXact_generator/ipyxact_parser' in .gitmodules
```Add as a submodule. Now recursive clone fails.
```
fatal: No url found for submodule path 'modules/CTU_CAN_FD/scripts/pyXact_generator/ipyxact_parser' in .gitmodules
```Bug fixingIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/157driver: handle SocketCAN mode switches2018-06-20T15:15:03ZMartin Jeřábekdriver: handle SocketCAN mode switches* [x] CAN_CTRLMODE_LISTENONLY
* [x] CAN_CTRLMODE_3_SAMPLES
* [x] CAN_CTRLMODE_FD (enable/disable FD)
* [x] CAN_CTRLMODE_PRESUME_ACK
* [x] CAN_CTRLMODE_FD_NON_ISO
* [x] CAN_CTRLMODE_ONE_SHOT* [x] CAN_CTRLMODE_LISTENONLY
* [x] CAN_CTRLMODE_3_SAMPLES
* [x] CAN_CTRLMODE_FD (enable/disable FD)
* [x] CAN_CTRLMODE_PRESUME_ACK
* [x] CAN_CTRLMODE_FD_NON_ISO
* [x] CAN_CTRLMODE_ONE_SHOTLinux driverMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/167Data length code test2018-07-14T21:43:23ZIlle, Ondrej, Ing.Data length code testAdd feature test, which will generate CAN 2.0 Frames with DLC < 8 and verify that all 8 bytes
of Data are sent! Then generate CAN Frame with DLC > 8, send it, and verify that only 8 bytes
were sent and received!Add feature test, which will generate CAN 2.0 Frames with DLC < 8 and verify that all 8 bytes
of Data are sent! Then generate CAN Frame with DLC > 8, send it, and verify that only 8 bytes
were sent and received!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/172Code coverage improvements2018-07-21T17:02:07ZIlle, Ondrej, Ing.Code coverage improvementsActual implementation of test logic is using standard "if" clause which is no very good since,
in case of error multiple lines are not executed and code coverage gets into red numbers.
The aim of this task is to use "assert" statement w...Actual implementation of test logic is using standard "if" clause which is no very good since,
in case of error multiple lines are not executed and code coverage gets into red numbers.
The aim of this task is to use "assert" statement where possible for implementation of tests.
This would cause (in case of feature tests) loss of generality since "o.outcome" can not be
asserted by assert statement! Possible solution for this problem might be rewriting the
tests to assume that test will fail by default and that when condition is satisfied, outcome
is set to desired value!Test maintenancehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/182Test linux driver on real HW2019-03-14T19:52:59ZMartin JeřábekTest linux driver on real HWThis is a direct continuation of #162. The question is - as this requires the bitstream, should this be run from CAN_FD_IP_Core pipeline or from zynq-can-sja1000-top?This is a direct continuation of #162. The question is - as this requires the bitstream, should this be run from CAN_FD_IP_Core pipeline or from zynq-can-sja1000-top?ISO conformance testingMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/200Bring-up GHDL functional coverage.2019-02-02T11:15:18ZIlle, Ondrej, Ing.Bring-up GHDL functional coverage.The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated ...The aim of this task is to bring up functional coverage with GHDL.
Main topics are:
1. [x] Write simple PSL cover statement into some of RTL codes.
2. [x] Execute test which activates this point.
3. [x] Show that PSL point was activated in a coverage output.
4. [x] Add PSL coverage gatherhing settings to config file
5. [x] Create PSL statement directly to directory with functional coverage without copyingFunctional coveragehttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/248tests: output does not respect verbosity settings2019-02-02T14:08:41ZMartin Jeřábektests: output does not respect verbosity settingsAfter switching to VUnit log lib, messages with all error levels are printed. In turn, the files with results are too huge and cannot be deployed to gitlab pages.
In the old vunit-enhancements branch it was solved by calling:
* show_all...After switching to VUnit log lib, messages with all error levels are printed. In turn, the files with results are too huge and cannot be deployed to gitlab pages.
In the old vunit-enhancements branch it was solved by calling:
* show_all(logger, display_handler);
* hide(logger, display_handler, debug); ...
I will look into it.Martin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/239Regmap gen saturation fix.2019-01-08T20:13:20ZIlle, Ondrej, Ing.Regmap gen saturation fix.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.Add fix for register map generator which will return all zeroes on read_data when adress in data_mux is saturated.ISO optimizationsIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/219Create wave file for registers2019-01-06T16:02:56ZIlle, Ondrej, Ing.Create wave file for registersAdd new wave file with all register values as they are implemented after automatic generation of register map.Add new wave file with all register values as they are implemented after automatic generation of register map.Test improvementshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/204SSP offset2019-01-06T10:30:16ZIlle, Ondrej, Ing.SSP offsetImplement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for S...Implement additional SW offset to Measured secondary sampling point.
Measured SSP OFFSET (trv_delay), can be still read from TRV_DELAY.
Higher bits of trv_delay register can be used for offset and offset control.
Following options for SSP offset:
1. Use only measured value
2. Use only SW offset.
3. Use measured value + SW offset.
Addition of trv_delay and SW SSP offset will be realized inside Bus Sampling
module, since shift registers for secondary sampling are implemented there.ISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/188swap set/reset priority for DOI2019-01-02T16:21:31ZMartin Jeřábekswap set/reset priority for DOIContinuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition w...Continuation of #187.
APB is access OK, but the problem would still occur on AXI/Avalon (or whichever bus which has one-cycle transactions). As a solution it would be enough to swap set/reset priority for DOI. The SW/HW race condition which it would introduce is still here, so nothing is lost.
Tasks:
- [x] change implementation
- [x] modify tests
- [x] modify documentationISO optimizationshttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/183driver: stuck in interrupt on RX buffer overrun2019-01-02T17:33:21ZMartin Jeřábekdriver: stuck in interrupt on RX buffer overrunMartin JeřábekMartin Jeřábekhttps://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/187Examine consecutive write data overrun and clear interrupt2018-09-11T14:51:27ZIlle, Ondrej, Ing.Examine consecutive write data overrun and clear interruptUpon overrun on RX Buffer, clear overrun flag is set. It is possible that if two consecutive memory
accesses to CMD[CDO] and INT_STAT (write to clear interrupt by overrun), this interrupt won't be cleared, since
overrun is cleared two cl...Upon overrun on RX Buffer, clear overrun flag is set. It is possible that if two consecutive memory
accesses to CMD[CDO] and INT_STAT (write to clear interrupt by overrun), this interrupt won't be cleared, since
overrun is cleared two clock cycles later.
Create testbench which will resolve this possibility!https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/156tx_arb_unit_test fails on 205th iteration2018-09-05T17:56:10ZMartin Jeřábektx_arb_unit_test fails on 205th iterationWhen TX arbitration unit test is run with high number of iterations, it eventually fails on "DUT and Model Frame valid not matching!".When TX arbitration unit test is run with high number of iterations, it eventually fails on "DUT and Model Frame valid not matching!".Test maintenanceIlle, Ondrej, Ing.Ille, Ondrej, Ing.https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core/-/issues/195TX Buffer explicit memory2018-10-31T20:22:24ZIlle, Ondrej, Ing.TX Buffer explicit memoryAs RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.As RX Buffer FIFO contains explicit inferred RAM wrapper, it might be good to do it the same way in TXT Buffers,
to use one entity wrappers for all RAMs / BRAMs. This wrapper might in future be replaced by hard-core RAM IP.ISO optimizations