GitLab

Added blocks for each register to make the assignment more readable.
Signed-off-by: Ille, Ondrej, Ing <illeondr@fel.cvut.cz>

component for register sub-modules.
This will be later added to
generator.

2. Converted pre-set of Frame Counters to clear only!

to command register.

in VHDL design.

interpreted correctly if given as boolean type.