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src: Resolve warnings from Vivado synthesis.

Closes #351

See merge request !333

     decrease power at expense of keeping data in previous value after
     the read has finished (instead of zeroeing). This does not mind since
     read data are defined as unknown from second cycle on after the read!
     So it is not in conflict with documenationt.

src: Fix invalid definition.

Closes #325

See merge request !332

src: Avoid using auto-gate for PC FSM. This should provide better

Closes #338

See merge request !331

This is good since when node becomes bus-off, PC FSM is not yet
in "reintegration wait state". Therefore, if command is issued sooner,
(e.g. still during EF which caused transition to bus off), it would
get lost without this handshake mechanism!

     timing performance!

Resolve "Split register list from RTL"

Closes #330

See merge request !330

If first detected bit is stuff bit, then we also must account it.
Otherwise, we force value recessive for one bit longer!!!

When sending first bit of ID recessive and we did not send
SOF, we must force stuff count value to 1 (not to 2), because
this accounts only for the value of first bit of ID!

Test must not skip stuff bits. Otherwise if stuff bit is corrupted
randomly, then it will also remain forcing the bus value to opposite
value during first bit of Error flag, thus REC will increment more!

SSP_OFFSET cant be longer than data bit time! Otherwise, we are gonna
sample in the next bit and generate bit error way earlier than we
inject bit error to the bus.

Furthermore, move declaration of "t_memory_reg" into
separate package so that they are not declared twice
when multiple memory maps are generated.

doc: Improve readme.

Closes #350

See merge request !329

# Conflicts:
#   README.md

doc: Improve readme.

Closes #350

See merge request !328