- 04 Apr, 2020 1 commit
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Ille, Ondrej, Ing. authored
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- 27 Mar, 2020 1 commit
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Ille, Ondrej, Ing. authored
src: Resolve warnings from Vivado synthesis. Closes #351 See merge request !333
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- 07 Mar, 2020 1 commit
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Ille, Ondrej, Ing. authored
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- 06 Mar, 2020 5 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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- 05 Mar, 2020 3 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
decrease power at expense of keeping data in previous value after the read has finished (instead of zeroeing). This does not mind since read data are defined as unknown from second cycle on after the read! So it is not in conflict with documenationt.
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Ille, Ondrej, Ing. authored
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- 04 Mar, 2020 1 commit
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Ille, Ondrej, Ing. authored
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- 25 Feb, 2020 2 commits
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Ille, Ondrej, Ing. authored
src: Fix invalid definition. Closes #325 See merge request !332
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Ille, Ondrej, Ing. authored
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- 18 Jan, 2020 6 commits
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Ille, Ondrej, Ing. authored
src: Avoid using auto-gate for PC FSM. This should provide better Closes #338 See merge request !331
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
This is good since when node becomes bus-off, PC FSM is not yet in "reintegration wait state". Therefore, if command is issued sooner, (e.g. still during EF which caused transition to bus off), it would get lost without this handshake mechanism!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
timing performance!
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- 17 Jan, 2020 16 commits
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Ille, Ondrej, Ing. authored
Resolve "Split register list from RTL" Closes #330 See merge request !330
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
If first detected bit is stuff bit, then we also must account it. Otherwise, we force value recessive for one bit longer!!!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
When sending first bit of ID recessive and we did not send SOF, we must force stuff count value to 1 (not to 2), because this accounts only for the value of first bit of ID!
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Ille, Ondrej, Ing. authored
Test must not skip stuff bits. Otherwise if stuff bit is corrupted randomly, then it will also remain forcing the bus value to opposite value during first bit of Error flag, thus REC will increment more!
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
SSP_OFFSET cant be longer than data bit time! Otherwise, we are gonna sample in the next bit and generate bit error way earlier than we inject bit error to the bus.
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
Furthermore, move declaration of "t_memory_reg" into separate package so that they are not declared twice when multiple memory maps are generated.
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Ille, Ondrej, Ing. authored
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- 13 Jan, 2020 4 commits
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Ille, Ondrej, Ing. authored
doc: Improve readme. Closes #350 See merge request !329
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Ille, Ondrej, Ing. authored
# Conflicts: # README.md
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
doc: Improve readme. Closes #350 See merge request !328
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