GitLab

Remove r0 on CAN 2.0 extended frame format! This should NOT be
treated as form error when Recessive is detected!

Swap test to check on receiver as on transmitter this is now
detected as bit error, not form error. Selectively enable/disable
FD support so that form error can be detected at correct spot!

In s_pc_r0_ext this is always CAN 2.0 frame with extended identifier,
therefore form error shall not be detected here!
This is not the same as r0_fd which really indicates CAN XL frame!

doc: minor clarifications.

Closes #356

See merge request !337

Resolve "Fix REC decrement"

Closes #355

See merge request !336

src: Fix Overload delimiter duration!

Closes #354

See merge request !335

src: Gate RTR flag when CAN FD flag is sampled!

Closes #352

See merge request !334

src: Resolve warnings from Vivado synthesis.

Closes #351

See merge request !333

     decrease power at expense of keeping data in previous value after
     the read has finished (instead of zeroeing). This does not mind since
     read data are defined as unknown from second cycle on after the read!
     So it is not in conflict with documenationt.

src: Fix invalid definition.

Closes #325

See merge request !332

src: Avoid using auto-gate for PC FSM. This should provide better

Closes #338

See merge request !331

This is good since when node becomes bus-off, PC FSM is not yet
in "reintegration wait state". Therefore, if command is issued sooner,
(e.g. still during EF which caused transition to bus off), it would
get lost without this handshake mechanism!

     timing performance!

Resolve "Split register list from RTL"

Closes #330

See merge request !330

If first detected bit is stuff bit, then we also must account it.
Otherwise, we force value recessive for one bit longer!!!