- 19 May, 2018 1 commit
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Ille, Ondrej, Ing. authored
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- 12 Mar, 2018 3 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
from the kernel header file
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Ille, Ondrej, Ing. authored
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- 06 Feb, 2018 2 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
32 bit bitfields and the name of the union is assembled from the sub-registers.
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- 01 Feb, 2018 1 commit
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Ille, Ondrej, Ing. authored
to use stack as lyx generator instead of stupid true false switching between beggining and end of the package
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- 27 Jan, 2018 3 commits
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
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Ille, Ondrej, Ing. authored
First working alpha version. Language functionality (VHDL, C) abstracted into set of classes with common ancestor, IP-XACT functionality abstracted into separate classes too.
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