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Also node 1 will end up in Overload (not error) frame.

Positive resynchronisation shall occur also when unit is receiver!

Remove r0 on CAN 2.0 extended frame format! This should NOT be
treated as form error when Recessive is detected!

Swap test to check on receiver as on transmitter this is now
detected as bit error, not form error. Selectively enable/disable
FD support so that form error can be detected at correct spot!

If first detected bit is stuff bit, then we also must account it.
Otherwise, we force value recessive for one bit longer!!!

Test must not skip stuff bits. Otherwise if stuff bit is corrupted
randomly, then it will also remain forcing the bus value to opposite
value during first bit of Error flag, thus REC will increment more!

SSP_OFFSET cant be longer than data bit time! Otherwise, we are gonna
sample in the next bit and generate bit error way earlier than we
inject bit error to the bus.

Furthermore, move declaration of "t_memory_reg" into
separate package so that they are not declared twice
when multiple memory maps are generated.