1. 27 Jul, 2019 1 commit
  2. 23 Jul, 2019 3 commits
  3. 12 Jul, 2019 1 commit
  4. 08 Jul, 2019 3 commits
  5. 07 Jul, 2019 1 commit
  6. 06 Jul, 2019 1 commit
  7. 02 Jul, 2019 2 commits
  8. 22 Jun, 2019 1 commit
  9. 21 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Use CRC init vector loading controlled by Protocol control FSM. · 0f1153da
      Ille, Ondrej, Ing. authored
      Init vector is not loaded on by edge on enable but by PC FSM. This
      allows removing special mux on datapath in Bit-destuffing. Thanks
      to this, when H-sync edge occurs in Idle right in Process pipeline
      stage, unit properly samples recessive and not dominant and measures
      length of arbitration field properly.
      
      CRC Init vector is always loaded in situations:
      1. In Intermission (first or second bit), does not mind being loaded
         twice. Can't be loaded in third one since this can already be SOF
         and first bit of calculation might be executed.
      2. Transfer to Idle after integration or reintegration.
      
      Note that there is always intermission after every frame so we are
      sure that init vector will get loaded! Loading post re-integration
      and integration is done just to be sure it is loaded after unit
      just joins the bus.
      0f1153da
  10. 20 Jun, 2019 1 commit
  11. 16 Jun, 2019 2 commits
  12. 14 Jun, 2019 4 commits
  13. 13 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Remove second bit time counters. · e27ab4b2
      Ille, Ondrej, Ing. authored
      Implemented sample control bypassing scheme which allows
      updating sample control right in first cycle after bit
      rate shift. Added extra load of expected segment length
      register in BRS.
      e27ab4b2
  14. 12 Jun, 2019 1 commit
    • Ille, Ondrej, Ing.'s avatar
      src: Add DFF to Bit Destuffing processing. · 68ae6173
      Ille, Ondrej, Ing. authored
      Enable CRC in Idle only after DOMINANT was sampled in Sample point,
      not during whole time when RX Data are dominant! Previous value is
      sampled anyway in bit destuffing and since it is first dominant,
      same_bits counter needs to be set to 1 anyway! So it will be set
      to 1 by rising edge on enable after DOMINANT is sampled and we are
      sure we go to BASE_ID.
      68ae6173
  15. 10 Jun, 2019 2 commits
  16. 09 Jun, 2019 1 commit
  17. 08 Jun, 2019 2 commits
  18. 06 Jun, 2019 1 commit
  19. 05 Jun, 2019 2 commits
  20. 02 Jun, 2019 5 commits
  21. 28 May, 2019 1 commit
  22. 25 May, 2019 2 commits
  23. 24 May, 2019 1 commit