1. 19 May, 2018 2 commits
  2. 24 Apr, 2018 1 commit
    • Ille, Ondrej, Ing.'s avatar
      Added fix of internal reset. · 9ed4c62a
      Ille, Ondrej, Ing. authored
      All components should be reset by "res_out" output of
      memory registers. Internally to memory registers,
      synchronised reset (res_n_sync) is connected via AND
      gate to SW reset (bit of MODE register).
      9ed4c62a
  3. 06 Apr, 2018 3 commits
  4. 26 Mar, 2018 1 commit
  5. 12 Mar, 2018 2 commits
  6. 07 Mar, 2018 1 commit
  7. 22 Feb, 2018 1 commit
  8. 21 Feb, 2018 2 commits
  9. 19 Feb, 2018 1 commit
  10. 17 Feb, 2018 1 commit
  11. 15 Feb, 2018 1 commit
  12. 10 Feb, 2018 1 commit
  13. 30 Jan, 2018 1 commit
  14. 18 Jan, 2018 1 commit
  15. 28 Dec, 2017 1 commit
  16. 27 Dec, 2017 2 commits
    • Ille, Ondrej, Ing.'s avatar
      Added Notification to the CAN Core about change of source · 9f0461b7
      Ille, Ondrej, Ing. authored
      TXT Buffer. This is needed for compatibility of "Frame Swapping"
      and "Retransmitt limit".
      
      If frame swapping is enabled then if retransmitt occurs, then
      change of the source buffer indicates that retransmit error counter
      should be erased, since other frame is being transmitted!
      In case that buffer does not change in retransmitt, the counter
      must be kept the same.
      In case that frame is transmitted succesfully and no retransmitt
      occurs ,the PRotocol control erases the the counter by itself.
      9f0461b7
    • Ille, Ondrej, Ing.'s avatar
      Added "Frame swapping" feature for new decision on which · 28ea57c5
      Ille, Ondrej, Ing. authored
      frame should be transmitted after losing arbitration or
      error frame.
      28ea57c5
  17. 20 Dec, 2017 3 commits
  18. 15 Dec, 2017 1 commit
  19. 13 Dec, 2017 1 commit
  20. 12 Dec, 2017 1 commit
  21. 11 Dec, 2017 3 commits
  22. 10 Dec, 2017 1 commit
  23. 08 Dec, 2017 1 commit
  24. 05 Dec, 2017 1 commit
  25. 04 Dec, 2017 1 commit
  26. 01 Dec, 2017 1 commit
  27. 29 Nov, 2017 1 commit
    • Ille, Ondrej, Ing.'s avatar
      Optimization of RX Data storing. · cfef3b2d
      Ille, Ondrej, Ing. authored
      From paralell logic vector sequential RAM is now
      used in Protocol controller. RX Buffer
      testbench accustomized, though still not passing!
      Protocol control testbench: TODO!!!
      cfef3b2d
  28. 27 Nov, 2017 1 commit
  29. 23 Nov, 2017 2 commits