GitLab

for negative values.

latest work.

Joined all test includes to single context.

Re-named CANComponents to can_components.

wrapper. Output is already selected CRC based on selector signal.

Used single adder for both counters and mux on input.
Added assert on mutual exclusion of simultaneous addition.
This should be always valid since "tran_valid" and "rec_valid"
occur in different part of CAN frame.

Synthesis was adding AND gates on each line after BRAM. This is not
desirable, direct output from memory must be taken!

Re-worked interrupt module to use explicit enable for
interrupt mask.

the same naming rules.

modules.

elements.

Resolve "Extend pyxact generator with VHDL access generation"

Closes #109

See merge request illeondr/CAN_FD_IP_Core!173