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Added TCL wave file for memory registers.

Added explicit warning to register descriptions. Some registers are

Closes #227

See merge request illeondr/CAN_FD_IP_Core!185

marked as "modify only when the core is off". This will hopefully
prevent users changing bit-rate during transmission :D

Merge branch '228-mode-rst-bit-does-not-autoclear-as-it-should-driver-is-not-functional-without-it' into 'master'

Fixed MODE[RST] does not autoclear.

Closes #228

See merge request illeondr/CAN_FD_IP_Core!184

re-generated register map.

Resolve "SSP offset"

Closes #204

See merge request illeondr/CAN_FD_IP_Core!183

handling function must be accustomized.

Added saturation on SSP delay.
Separated TX,RX edge detection to stand-alone modules.

Adapt canbench-sw and CTU_CAN_FD Vivado component to match sources after 207-design-decoupling merge

Closes #226 and #224

See merge request illeondr/CAN_FD_IP_Core!180

testfw: improvements

See merge request illeondr/CAN_FD_IP_Core!181

Reapplied, as it got lost for some reason ...

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>

Swapped priority of set/reset for DOI interrupt. Added

Closes #188

See merge request illeondr/CAN_FD_IP_Core!177

constant with definition of Interrupt Set/Clear priorities.

Resolve "add registers for reading current timestamp"

Closes #208

See merge request illeondr/CAN_FD_IP_Core!176

to do all the work. Voila, miracle of register map generator.

Resolve "Design decoupling"

Closes #207

See merge request illeondr/CAN_FD_IP_Core!175

not support context. Used context only for testbench codes.

for negative values.

latest work.